Abstract: A transmitter component includes an input terminal and a first semiconductor portion with doped regions of a control-side interface circuit. The control-side interface circuit converts a digital input signal received at the input terminal into a transmit radio frequency signal. A control-side metallization structure on at least one of two horizontal main surfaces of the first semiconductor portion includes at least a portion of a control-side antenna structure that emits the transmit radio frequency signal as radio wave. A transceiver circuit may include the transmitter component and a receiver component.

Abstract: A calibration method for a phased array system comprises sequentially injecting a tone into a first plurality of antenna elements of an antenna array, receiving the tone by a second plurality of antenna elements of the antenna array through parasitic coupling between the first plurality of antenna elements and the second plurality of antenna elements, measuring a plurality of phase errors between the first plurality of antenna elements and the second plurality of antenna elements, populating a lookup table with the plurality of phase errors, and calibrating a plurality of phase shifters associated with a plurality of channels in the phased array system using the plurality of phase errors in the lookup table.

Abstract: A transmitter component includes an input terminal and a first semiconductor portion with doped regions of a control-side interface circuit. The control-side interface circuit converts a digital input signal received at the input terminal into a transmit radio frequency signal. A control-side metallization structure on at least one of two horizontal main surfaces of the first semiconductor portion includes at least a portion of a control-side antenna structure that emits the transmit radio frequency signal as radio wave. A transceiver circuit may include the transmitter component and a receiver component.

Abstract: A phased-locked loop (PLL) circuit with an injection locked digital digitally controlled oscillator (ILD) that has an ILD control input element, an ILD injection input element and an ILD output element. The PLL circuit also includes an adaptive control unit (ACU), wherein the ACU is configured to receive an error signal and is configured to output an ILD control word. The ILD control input element is configured to receive the ILD control word, and the ILD control word may set a natural oscillation frequency of the ILD. The ILD is further configured to output a first output signal from the ILD output element, where the natural oscillation frequency may set a frequency of the first output signal.

Abstract: A circuit includes an amplifier and pre-distortion circuit. The amplifier amplifies a modulated signal. The signal pre-distortion circuit performs a feed-forward pre-distortion of the modulated signal in a signal path in which the amplifier resides. The signal pre-distortion circuit includes: i) an envelope detector configured operative to provide an envelope information describing an envelope of the modulated signal; and ii) a built-in test circuit that determines distortion information describing a distortion in the signal path caused by amplitude variations. The signal pre-distortion circuit performs the feed-forward pre-distortion of the modulated signal on the basis of the distortion information.

Abstract: A calibration method for a phased array system comprises sequentially injecting a tone into a first plurality of antenna elements of an antenna array, receiving the tone by a second plurality of antenna elements of the antenna array through parasitic coupling between the first plurality of antenna elements and the second plurality of antenna elements, measuring a plurality of phase errors between the first plurality of antenna elements and the second plurality of antenna elements, populating a lookup table with the plurality of phase errors, and calibrating a plurality of phase shifters associated with a plurality of channels in the phased array system using the plurality of phase errors in the lookup table.

Abstract: Techniques (implemented in circuit arrangements, methods, computer instructions) are disclosed which permit digital pre-distortion for amplifiers. A common signal source provides a common analog signal from a digital input signal; a plurality of amplifiers amplifies a split signal which is a split version of the common analog signal; a built-in test circuit is configured to provide distortion information associated to distortion affecting the amplifier. The common signal source implements a signal conditioner to perform, in a signal path of the digital input signal, a feed-forward pre-distortion of the digital input signal according to a pre-distortion relationship mapping the digital input signal onto a pre-distorted version. The signal conditioner is configured to adjust the pre-distortion relationship in dependence on the distortion information.

Abstract: A phased-locked loop (PLL) circuit with an injection locked digital digitally controlled oscillator (ILD) that has an ILD control input element, an ILD injection input element and an ILD output element. The PLL circuit also includes an adaptive control unit (ACU), wherein the ACU is configured to receive an error signal and is configured to output an ILD control word. The ILD control input element is configured to receive the ILD control word, and the ILD control word may set a natural oscillation frequency of the ILD. The ILD is further configured to output a first output signal from the ILD output element, where the natural oscillation frequency may set a frequency of the first output signal.

Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.

Abstract: Techniques (implemented in circuit arrangements, methods, computer instructions) are disclosed which permit digital pre-distortion for amplifiers. A common signal source provides a common analog signal from a digital input signal; a plurality of amplifiers amplifies a split signal which is a split version of the common analog signal; a built-in test circuit is configured to provide distortion information associated to distortion affecting the amplifier. The common signal source implements a signal conditioner to perform, in a signal path of the digital input signal, a feed-forward pre-distortion of the digital input signal according to a pre-distortion relationship mapping the digital input signal onto a pre-distorted version. The signal conditioner is configured to adjust the pre-distortion relationship in dependence on the distortion information.

Abstract: A circuit includes an amplifier and pre-distortion circuit. The amplifier amplifies a modulated signal. The signal pre-distortion circuit performs a feed-forward pre-distortion of the modulated signal in a signal path in which the amplifier resides. The signal pre-distortion circuit includes: i) an envelope detector configured operative to provide an envelope information describing an envelope of the modulated signal; and ii) a built-in test circuit that determines distortion information describing a distortion in the signal path caused by amplitude variations. The signal pre-distortion circuit performs the feed-forward pre-distortion of the modulated signal on the basis of the distortion information.

Abstract: Devices and methods determining phase offsets are disclosed. A first test signal is transmitted from a first RF circuit part to a second RF circuit part, where a phase difference between the first test signal and a reference signal (ref) is measured. A second test signal is transmitted from the second RF circuit part to the first RF circuit part, where a second phase difference between the second test signal and the reference signal (ref) is measured. Phase offsets of a connection between the first and second circuit parts or of a line supplying the reference signal are determined based on the first and second phase differences.

Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.

Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.

Abstract: A pulse width modulation system comprises an analog component and a digital component. The analog component operates to separate a local oscillator signal with different phase shifts and introduce an offset (i.e., a time delay) to analog signals being receive at an input with a tuning operation that fine tunes in the analog signals in the analog (continuous time) domain. The analog component comprises a plurality of analog delay lines that respectively process carrier signals having a different phase shifts. Digital delay lines convert the analog signals to digital square waves with the same time delay and at the same resolution as the analog output signal.

Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.

Abstract: A signal detector device and method includes a quadrature demodulator configured to receive an input signal, a first reference signal, and a second reference signal in quadrature with the first reference signal, the quadrature demodulator further configured to produce a plurality of output signals from the input signal and the first and the second reference signal, the plurality of output signals indicating the amplitude and phase of the input signal, and one or more inverting circuits, the inverting circuits having a first and a second programmable output polarity, the plurality of output signals being output by the quadrature demodulator when the inverting circuits are set to the first programmable output polarity, the plurality of output signals being inverted and output by the quadrature demodulator when the inverting circuits are set to the second programmable output polarity.

Abstract: Devices and methods determining phase offsets are disclosed. A first test signal is transmitted from a first RF circuit part to a second RF circuit part, where a phase difference between the first test signal and a reference signal (ref) is measured. A second test signal is transmitted from the second RF circuit part to the first RF circuit part, where a second phase difference between the second test signal and the reference signal (ref) is measured. Phase offsets of a connection between the first and second circuit parts or of a line supplying the reference signal are determined based on the first and second phase differences.

Abstract: According to an embodiment, a radio frequency device includes a phase locked loop circuit, and an automatic gain control circuit, where an output of an automatic gain control circuit is coupled to a reference signal input of the phase locked loop circuit.

Abstract: In accordance with an embodiment a beamforming circuit having a radio frequency (RF) front end and a plurality of beamforming delay circuits coupled to the RF front end. Each of the plurality of beamforming delay circuits includes a common delay circuit and a plurality of individual delay circuits coupled to the common delay circuit. Each of the individual delay circuits are configured to be coupled to an antenna element of a beamforming array.