Patents by Inventor Marc Tremblay

Marc Tremblay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7584346
    Abstract: One embodiment of the present invention provides a system that supports different modes of multi-threaded speculative execution on a processor. The system starts with two or more threads executing in a first multi-threaded speculative-execution mode. The system then switches to a second multi-threaded speculative-execution mode by configuring circuits in the processor to enable a second multi-threaded speculative-execution mode. After configuring the circuits, the system next switches the threads from executing in the first multi-threaded speculative-execution mode to executing in the second multi-threaded speculative-execution mode.
    Type: Grant
    Filed: January 25, 2007
    Date of Patent: September 1, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Shailender Chaudhry, Marc Tremblay, Paul Caprioli
  • Patent number: 7574588
    Abstract: One embodiment of the present invention provides a system that facilitates interleaved execution of a head thread and a speculative thread within a single processor pipeline. The system operates by executing program instructions using the head thread, and by speculatively executing program instructions in advance of the head thread using the speculative thread, wherein the head thread and the speculative thread execute concurrently through time-multiplexed interleaving in the single processor pipeline.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: August 11, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Shailender Chaudhry, Marc Tremblay
  • Patent number: 7571304
    Abstract: One embodiment of the present invention provides a system which creates multiple checkpoints in a processor that supports speculative-execution. The system starts by issuing instructions for execution in program order during execution of a program in a normal-execution mode. Upon encountering a launch condition during an instruction which causes a processor to enter execute-ahead mode, the system performs an initial checkpoint and commences execution of instructions in execute-ahead mode. Upon encountering a predefined condition during execute-ahead mode, the system generates an additional checkpoint and continues to execute instructions in execute-ahead mode. Generating the additional checkpoint allows the processor to return to the additional checkpoint, instead of the previous checkpoint, if the processor subsequently encounters a condition that requires the processor to return to a checkpoint.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: August 4, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Shailender Chaudhry, Marc Tremblay, Paul Caprioli
  • Patent number: 7565511
    Abstract: A technique for operating a computing apparatus includes allocating a working register file entry corresponding to a register in a working register file when an instruction referencing the register proceeds through a particular stage of the computing apparatus. The technique maintains the working register file entry until at least a predetermined number of subsequent instructions have similarly proceeded through the particular stage.
    Type: Grant
    Filed: June 22, 2006
    Date of Patent: July 21, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Shailender Chaudhry, Quinn A. Jacobson, Marc Tremblay
  • Patent number: 7523266
    Abstract: One embodiment of the present invention provides a system that enforces memory reference ordering requirements, such as Total Store Ordering (TSO), at a Level 1 (L1) cache in a multiprocessor. During operation, while executing instructions in a speculative-execution mode, the system receives an invalidation signal for a cache line at the L1 cache wherein the invalidation signal is received from a cache-coherence system within the multiprocessor. In response to the invalidation signal, if the cache line exists in the L1 cache, the system examines a load-mark in the cache line, wherein the load-mark being set indicates that the cache line has been loaded from during speculative execution. If the load-mark is set, the system fails the speculative-execution mode and resumes a normal-execution mode from a checkpoint.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: April 21, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Shailender Chaudhry, Marc Tremblay
  • Patent number: 7519775
    Abstract: One embodiment of the present invention provides a system that enforces memory-reference ordering requirements at an L2 cache. During operation, the system receives a load at the L2 cache, wherein the load previously caused a miss at an L1cache. Upon receiving the load, the system performs a lookup for the load in reflections of store buffers associated with other L1 caches. These reflections are located at the L2 cache, and each reflection contains addresses for stores in a corresponding store buffer associated with an L1 cache, and possibly contains data that was overwritten by the stores. If the lookup generates a hit, which indicates that the load may potentially interfere with a store, the system causes the load to wait to execute until the store commits.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: April 14, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Shailender Chaudhry, Marc Tremblay
  • Patent number: 7509481
    Abstract: Mechanisms have been developed for providing great flexibility in processor instruction handling, sequencing and execution. In particular, it has been discovered that a programmable pre-decode mechanism can be employed to alter the behavior of a processor. For example, pre-decode hints for sequencing, synchronization or speculation control may altered or mappings of ISA instructions to native instructions or operation sequences may be altered. Such techniques may be employed to adapt a processor implementation (in the field) to varying memory models, implementations or interfaces or to varying memory latencies or timing characteristics. Similarly, such techniques may be employed to adapt a processor implementation to correspond to an extended/adapted instruction set architecture. In some realizations, instruction pre-decode functionality may be adapted at processor run-time to handle or mitigate a timing, concurrency or speculation issue.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: March 24, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Shailender Chaudhry, Paul Caprioli, Quinn A. Jacobson, Marc Tremblay
  • Patent number: 7500086
    Abstract: One embodiment of the present invention supports execution of a start transactional execution (STE) instruction, which marks the beginning of a block of instructions to be executed transactionally. Upon encountering the STE instruction during execution of a program, the system commences transactional execution of the block of instructions following the STE instruction. Changes made during this transactional execution are not committed to the architectural state of the processor until the transactional execution successfully completes.
    Type: Grant
    Filed: December 6, 2005
    Date of Patent: March 3, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Marc Tremblay, Shailender Chaudhry, Quinn A. Jacobson
  • Patent number: 7490228
    Abstract: A processor including a large register file utilizes a dirty bit storage coupled to the register file and a dirty bit logic that controls resetting of the dirty bit storage. The dirty bit logic determines whether a register or group of registers in the register file has been written since the process was loaded or the context was last restored and, if written generates a value in the dirty bit storage that designates the written condition of the register or group of registers. When the context is next saved, the dirty bit logic saves a particular register or group of registers when the dirty bit storage indicates that a register or group of registers was written. If the register or group of registers was not written, the context is switched without saving the register or group of registers. The dirty bit storage is initialized when a process is loaded or the context changes.
    Type: Grant
    Filed: March 6, 2006
    Date of Patent: February 10, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Marc Tremblay, William Joy
  • Patent number: 7490229
    Abstract: One embodiment of the present invention provides a system that facilitates storing results of resolvable branches during speculative execution, and then using the results to predict the same branches during non-speculative execution. During operation, the system executes code within a processor. Upon encountering a stall condition, the system speculatively executes the code from the point of the stall, without committing results of the speculative execution to the architectural state of the processor. Upon encountering a branch instruction that is resolved during speculative execution, the system stores the result of the resolved branch in a branch queue, so that the result can be subsequently used to predict the branch during non-speculative execution.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: February 10, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Marc Tremblay, Shailender Chaudhry, Quinn A. Jacobson
  • Patent number: 7484080
    Abstract: One embodiment of the present invention provides a system that facilitates deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order. During a normal execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint that can subsequently be used to return execution of the program to the point of the instruction. Next, the system executes the instruction and subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order. Upon encountering a store during the execute-ahead mode, the system determines if the store buffer is full. If so, the system prefetches a cache line for the store, and defers execution of the store.
    Type: Grant
    Filed: April 11, 2005
    Date of Patent: January 27, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Shailender Chaudhry, Marc Tremblay, Paul Caprioli
  • Patent number: 7469334
    Abstract: One embodiment of the present invention provides a system that facilitates a fast execution restart following speculative execution. During normal operation of the system, a processor executes code on a non-speculative mode. Upon encountering a stall condition, the system checkpoints the state of the processor and executes the code in a speculative mode from the point of the stall. As the processor commences execution in speculative mode, it stores copies of instructions as they are issued into a recovery queue. When the stall condition is ultimately resolved, execution in non-speculative mode is recommenced and the execution units are initially loaded with instructions from the recovery queue, thereby avoiding the delay involved in waiting for instructions to propagate through the fetch and the decode stages of the pipeline. At the same time, the processor begins fetching subsequent instructions following the last instruction in the recovery queue.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: December 23, 2008
    Assignee: Sun Microsystems, Inc.
    Inventors: Shailender Chaudhry, Marc Tremblay, Quinn A. Jacobson
  • Patent number: 7437534
    Abstract: A Very Long Instruction Word (VLIW) processor having a plurality of functional units includes a multi-ported register file that is divided into a plurality of separate register file segments, each of the register file segments being associated to one of the plurality of functional units. The register file segments are partitioned into local registers and global registers. The global registers are read and written by all functional units. The local registers are read and written only by a functional unit associated with a particular register file segment. The local registers and global registers are addressed using register addresses in an address space that is separately defined for a register file segment/functional unit pair. The global registers are addressed within a selected global register range using the same register addresses for the plurality of register file segment/functional unit pairs.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: October 14, 2008
    Assignee: Sun Microsystems, Inc.
    Inventors: Marc Tremblay, William N. Joy
  • Patent number: 7430653
    Abstract: A pipelined instruction dispatch or grouping circuit allows instruction dispatch decisions to be made over multiple processor cycles. In one embodiment, the grouping circuit performs resource allocation and data dependency checks on an instruction group, based on a state vector which includes representation of source and destination registers of instructions within said instruction group and corresponding state vectors for instruction groups of a number of preceding processor cycles.
    Type: Grant
    Filed: August 2, 1999
    Date of Patent: September 30, 2008
    Assignee: Sun Microsystems, Inc.
    Inventor: Marc Tremblay
  • Patent number: 7418577
    Abstract: One embodiment of the present invention provides a system that supports executing a fail instruction, which terminates transactional execution of a block of instructions. During operation, the system facilitates transactional execution of a block of instructions within a program, wherein changes made during the transactional execution are not committed to the architectural state of the processor until the transactional execution successfully completes. If a fail instruction is encountered during this transactional execution, the system terminates the transactional execution without committing results of the transactional execution to the architectural state of the processor.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: August 26, 2008
    Assignee: Sun Microsystems, Inc.
    Inventors: Marc Tremblay, Shailender Chaudhry, Quinn A. Jacobson
  • Publication number: 20080189531
    Abstract: One embodiment of the present invention provides a system that prevents data hazards during simultaneous speculative threading. The system starts by executing instructions in an execute-ahead mode using a first thread. While executing instructions in the execute-ahead mode, the system maintains dependency information for each register indicating whether the register is subject to an unresolved data dependency. Upon the resolution of a data dependency during execute-ahead mode, the system copies dependency information to a speculative copy of the dependency information. The system then commences execution of the deferred instructions in a deferred mode using a second thread.
    Type: Application
    Filed: February 6, 2007
    Publication date: August 7, 2008
    Inventors: Shailender Chaudhry, Paul Caprioli, Marc Tremblay
  • Patent number: 7398355
    Abstract: One embodiment of the present invention provides a system that avoids locks by transactionally executing critical sections. During operation, the system receives a program which includes one or more critical sections which are protected by locks. Next, the system modifies the program so that the critical sections which are protected by locks are executed transactionally without acquiring locks associated with the critical sections.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: July 8, 2008
    Assignee: Sun Microsystems, Inc.
    Inventors: Mark S. Moir, Marc Tremblay, Shailender Chaudhry
  • Patent number: 7389383
    Abstract: One embodiment of the present invention provides a system that facilitates selectively unmarking load-marked cache lines during transactional program execution, wherein load-marked cache lines are monitored during transactional execution to detect interfering accesses from other threads. During operation, the system encounters a release instruction during transactional execution of a block of instructions. In response to the release instruction, the system modifies the state of cache lines, which are specially load-marked to indicate they can be released from monitoring, to account for the release instruction being encountered. In doing so, the system can potentially cause the specially load-marked cache lines to become unmarked. In a variation on this embodiment, upon encountering a commit-and-start-new-transaction instruction, the system modifies load-marked cache lines to account for the commit-and-start-new-transaction instruction being encountered.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: June 17, 2008
    Assignee: Sun Microsystems, Inc.
    Inventors: Marc Tremblay, Quinn A. Jacobson, Shailender Chaudhry, Mark S. Moir, Maurice P. Herlihy
  • Patent number: 7366880
    Abstract: One embodiment of the present invention provides a system that predicts a result produced by a section of code in order to support speculative program execution. The system begins by executing the section of code using a head thread in order to produce a result. Before the head thread produces the result, the system generates a predicted result to be used in place of the result. Next, the system allows a speculative thread to use the predicted result in speculatively executing subsequent code that follows the section of code. After the head thread finishes executing the section of code, the system determines if a difference between the predicted result and the result generated by the head thread has affected execution of the speculative thread. If so, the system executes the subsequent code again using the result generated by the head thread. If not, the system performs a join operation to merge state associated with the speculative thread with state associated with the head thread.
    Type: Grant
    Filed: January 25, 2006
    Date of Patent: April 29, 2008
    Assignee: Sun Microsystems, Inc.
    Inventors: Shailender Chaudhry, Marc Tremblay
  • Patent number: 7360028
    Abstract: A method and apparatus for performing a store-to-instruction-space instruction are provided. A unique opcode indicates that a data value is to be written to an instruction space in main memory. The instruction is received and executed. After the instruction space is modified to contain the data value, further processing is performed to ensure coherence between main memory and an instruction cache.
    Type: Grant
    Filed: May 5, 2000
    Date of Patent: April 15, 2008
    Assignee: Sun Microsystems, Inc.
    Inventor: Marc Tremblay