Abstract: The present invention relates to monitors. In order to facilitate mounting a monitor, a suspendable monitor (10) is provided for a ceiling suspended monitor system. The suspendable monitor comprises a video display (12), a structural frame (14), and a system interface (16). The video display is mounted to a front surface (18) of the structural frame. The system interface is mounted to the structural frame at one end and mountable to the ceiling suspended monitor system at the other end for suspending the suspendable monitor.

Abstract: The present invention relates to monitors. In order to facilitate mounting a monitor, a suspendable monitor (10) is provided for a ceiling suspended monitor system. The suspendable monitor comprises a video display (12), a structural frame (14), and a system interface (16). The video display is mounted to a front surface (18) of the structural frame. The system interface is mounted to the structural frame at one end and mountable to the ceiling suspended monitor system at the other end for suspending the suspendable monitor.

Abstract: A time discrete filter comprises a sampling rate converter provided with an input and an output, and a down-sampler having a down-sampling factor nd. The time discrete filter further comprises an up-sampler having an up-sampling factor nu, whereby the up-sampler is coupled to the converter input, and the converter output is coupled to the down-sampler. It has been found that if a sampling rate conversion operation is preceded by an up-sampling operation and only after the conversion is followed by a down-sampling operation to a wanted sampling frequency, that then the complexity in terms of the ultimate number of calculations, in particular multiplications and additions, is reduced. This leads to a decrease of the number of instructions per second which is a measure for the complexity of a Digital Signal Processing (DSP) algorithm.

Abstract: Sample rate converters (12) for converting input sample rates (F81) of signals into output sample rates (Fs4) are provided with sample rate adapters (3,6) for adapting (basic idea) intermediate sample rates (Fs2) such that output sample rates (Fs4) are larger (upsampling) or smaller (downsampling) than input sample rates (F81), to reduce their complexity and to avoid bookkeeping and structure switching problems. Sample rate adapters (3,6) in the form of variable sample rate decreasers (3) allow the sample rate converters (12) to be used in video applications requiring DC-out being equal to DC-in. Sample rate adapters (3,6) in the form of variable sample rate increasers (6) allow the sample rate converters (12) to be used in audio applications.

Abstract: A DC-offset correction circuit (I1, Q1) for a low-IF or zero-IF receiver, comprises a DC-offset control loop (O1, O2) embodied by: a summing device (9-1, 9-2) having a signal path input (10-1, 10-2), a DC control input (11-1, 11-2), and a summing output (12-1, 12-2); and an offset determining means (15-1, 15-2) coupled between the summing output (12-1, 12-2) and the DC control input of the summing device (9-1, 9-2). The DC-offset correction circuit (I1, Q1) further comprises a DC blocking circuit (17-1, 17-2) coupled to the summing output (12-1, 12-2) of the summing device (9-1, 9-2) and having a DC blocking output (18-1, 18-2) for providing an offset corrected output signal. The DC-offset control loop (O1, O2) and the DC blocking circuit (17-1, 17-2) advantageously interact in correcting DC offset.

Abstract: A time discrete filter comprises a sampling rate converter provided with an input and an output, and a down-sampler having a down-sampling factor nd. The time discrete filter further comprises an up-sampler having an up-sampling factor nu, whereby the up-sampler is coupled to the converter input, and the converter output is coupled to the down-sampler. It has been found that if a sampling rate conversion operation is preceded by an up-sampling operation and only after the conversion is followed by a down-sampling operation to a wanted sampling frequency, that then the complexity in terms of the ultimate number of calculations, in particular multiplications and additions, is reduced. This leads to a decrease of the number of instructions per second which is a measure for the complexity of a Digital Signal Processing (DSP) algorithm.

Abstract: Sample rate converters are known, and are used to convert a signal with a first sample rate (sampling frequency) into a signal with a second sample rate (sampling frequency). To obtain a flexible sample rate converter with sampling frequencies that are not known beforehand, until now only sample rate converters with very high intermediate sampling frequencies are known. The invention provides a flexible sample rate converter, which is able to handle unknown input and output sampling frequencies. This is achieved by using polyphase decomposition filter means in combination with interpolation means.

Abstract: A DC-offset correction circuit (I1, Q1) for a low-IF or zero-IF receiver, comprises a DC-offset control loop (O1, O2) embodied by: a summing device (9-1, 9-2) having a signal path input (10-1, 10-2), a DC control input (11-1, 11-2), and a summing output (12-1, 12-2); and an offset determining means (15-1, 15-2) coupled between the summing output (12-1, 12-2) and the DC control input of the summing device (9-1, 9-2). The DC-offset correction circuit (I1, Q1) further comprises a DC blocking circuit (17-1, 17-2) coupled to the summing output (12-1, 12-2) of the summing device (9-1, 9-2) and having a DC blocking output (18-1, 18-2) for providing an offset corrected output signal. The DC-offset control loop (O1, O2) and the DC blocking circuit (17-1, 17-2) advantageously interact in correcting DC offset.