Patents by Inventor Marcel A. Wall
Marcel A. Wall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20260005081Abstract: Hybrid glass and organic substrates, devices and systems formed thereon, and methods of forming the same, are disclosed herein. In one example, a substrate includes a glass layer and an organic frame around the glass layer, where the organic frame includes a polyimide.Type: ApplicationFiled: June 28, 2024Publication date: January 1, 2026Applicant: Intel CorporationInventors: Ehsan Zamani, Seyyed Yahya Mousavi, Manohar Konchady, Whitney M. Bryks, Yi Cao, Gang Duan, Darko Grujicic, Thomas S. Heaton, Andrew Matthew Jimenez, Jesse Jones, Shayan Kaviani, Jieying Kong, Shuqi Lai, Yi Li, Minglu Liu, Sandrine Lteif, Mahdi Mohammadighaleni, Tchefor T. Ndukum, Son Van Nguyen, Srinivas Venkata Ramanuja Pietambaram, Dilan Seneviratne, Rengarajan Shanmugam, Joshua J. Stacey, Elham Tavakoli, David Vickery, Marcel A. Wall, Yekan Wang, Anqi Zhang, James Kayode Ofuegbe, Zhixin Xie, Jung Kyu Han
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Patent number: 12476175Abstract: Glass substrates having transverse capacitors for use with semiconductor packages and related methods are disclosed. An example semiconductor package includes a glass substrate having a through glass via between a first surface and a second surface opposite the first surface. A transverse capacitor is located in the through glass via. The transverse capacitor includes a dielectric material positioned in a first portion of the through glass via, a first barrier/seed layer positioned in a second portion of the through glass via, and a first conductive material positioned in a third portion of the through glass via.Type: GrantFiled: September 24, 2021Date of Patent: November 18, 2025Assignee: Intel CorporationInventors: Benjamin T. Duong, Srinivas V. Pietambaram, Aleksandar Aleksov, Helme Castro De La Torre, Kristof Darmawikarta, Darko Grujicic, Sashi S. Kandanur, Suddhasattwa Nad, Rengarajan Shanmugam, Thomas I. Sounart, Marcel A. Wall
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Publication number: 20240186264Abstract: In one embodiment, an apparatus includes a glass substrate, a metal, and a polymeric layer between the metal and the glass substrate. The polymeric layer includes polymer molecules with an R1 group, an R2 group, a polymer backbone between the R1 group and R2 group, and an R3 group side-attached to the polymer backbone. The polymeric layer is bonded to the glass substrate via the R1 groups and bonded to the metal via the R2 groups.Type: ApplicationFiled: December 2, 2022Publication date: June 6, 2024Applicant: Intel CorporationInventors: Yi Yang, Eungnak Han, Suddhasattwa Nad, Marcel A. Wall
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Publication number: 20230402368Abstract: Techniques for thin-film resistors in vias are disclosed. In the illustrative embodiment, thin-film resistors are formed in through-glass vias of a glass substrate of an interposer. The thin-film resistors do not take up a significant amount of area on a layer of the interposer, as the thin-film resistor extends vertically through a via rather than horizontally on a layer of the interposer. The thin-film resistors may be used for any suitable purpose, such as power dissipation or voltage control, current control, as a pull-up or pull-down resistor, etc.Type: ApplicationFiled: June 10, 2022Publication date: December 14, 2023Applicant: Intel CorporationInventors: Benjamin T. Duong, Brian P. Balch, Kristof Darmawikarta, Darko Grujicic, Suddhasattwa Nad, Xing Sun, Marcel A. Wall, Yi Yang
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Publication number: 20230095846Abstract: Glass substrates having transverse capacitors for use with semiconductor packages and related methods are disclosed. An example semiconductor package includes a glass substrate having a through glass via between a first surface and a second surface opposite the first surface. A transverse capacitor is located in the through glass via. The transverse capacitor includes a dielectric material positioned in a first portion of the through glass via, a first barrier/seed layer positioned in a second portion of the through glass via, and a first conductive material positioned in a third portion of the through glass via.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Inventors: Benjamin T. Duong, Srinivas V. Pietambaram, Aleksandar Aleksov, Helme Castro De La Torre, Kristof Darmawikarta, Darko Grujicic, Sashi S. Kandanur, Suddhasattwa Nad, Rengarajan Shanmugam, Thomas I. Sounart, Marcel A. Wall
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Patent number: 11291122Abstract: Embodiments of the present disclosure describe techniques for providing an apparatus with a substrate provided with plasma treatment. In some instances, the apparatus may include a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus. The metal layer may be provided in response to a plasma treatment of the surface with a functional group containing a gas (e.g., nitrogen-based gas), to provide absorption of a transition metal catalyst into the surface, and subsequent electroless plating of the surface with a metal. The transition metal catalyst is to enhance electroless plating of the surface with the metal. Other embodiments may be described and/or claimed.Type: GrantFiled: September 22, 2017Date of Patent: March 29, 2022Assignee: Intel CorporationInventors: Darko Grujicic, Rengarajan Shanmugam, Sandeep Gaan, Adrian Bayraktaroglu, Roy Dittler, Ke Liu, Suddhasattwa Nad, Marcel A. Wall, Rahul N. Manepalli, Ravindra V. Tanikella
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Patent number: 11177232Abstract: Techniques and mechanisms for bonding structures of a circuit device with a monolayer. In an embodiment, a patterned metallization layer or a first dielectric layer includes a first surface portion. The first surface portion is exposed to first molecules which each include a first head group and a first end group which is substantially non-reactive with the first head group. The first head groups attach to the first portion to form a first self-assembled monolayer, which is subsequently reacted with second molecules to form a second monolayer comprising moieties of the first molecules. In another embodiment, the first head group comprises a first moiety comprising a sulfur atom or a nitrogen atom, where the first end group comprises one of an acid moiety, an acid anhydride moiety, an aliphatic alcohol moiety, an aromatic alcohol moiety, or an unsaturated hydrocarbon moiety.Type: GrantFiled: April 2, 2018Date of Patent: November 16, 2021Assignee: Intel CorporationInventors: Suddhasattwa Nad, Rahul N. Manepalli, Marcel A. Wall
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Publication number: 20200245472Abstract: Embodiments of the present disclosure describe techniques for providing an apparatus with a substrate provided with plasma treatment. In some instances, the apparatus may include a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus. The metal layer may be provided in response to a plasma treatment of the surface with a functional group containing a gas (e.g., nitrogen-based gas), to provide absorption of a transition metal catalyst into the surface, and subsequent electroless plating of the surface with a metal. The transition metal catalyst is to enhance electroless plating of the surface with the metal. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 22, 2017Publication date: July 30, 2020Inventors: Darko GRUJICIC, Rengarajan SHANMUGAM, Sandeep GAAN, Adrian BAYRAKTAROGLU, Roy DITTLER, Ke LIU, Suddhasattwa NAD, Marcel A. WALL, Rahul N. MANEPALLI, Ravindra V. TANIKELLA
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Publication number: 20190229082Abstract: Techniques and mechanisms for bonding structures of a circuit device with a monolayer. In an embodiment, a patterned metallization layer or a first dielectric layer includes a first surface portion. The first surface portion is exposed to first molecules which each include a first head group and a first end group which is substantially non-reactive with the first head group. The first head groups attach to the first portion to form a first self-assembled monolayer, which is subsequently reacted with second molecules to form a second monolayer comprising moieties of the first molecules. In another embodiment, the first head group comprises a first moiety comprising a sulfur atom or a nitrogen atom, where the first end group comprises one of an acid moiety, an acid anhydride moiety, an aliphatic alcohol moiety, an aromatic alcohol moiety, or an unsaturated hydrocarbon moiety.Type: ApplicationFiled: April 2, 2018Publication date: July 25, 2019Applicant: Intel CorporationInventors: Suddhasattwa Nad, Rahul N. Manepalli, Marcel A. Wall
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Publication number: 20170176173Abstract: Described herein are devices and techniques for measuring a thickness of a surface layer. A device can include a detector, a processor, and a memory. The detector can be arranged to receive reflected light from a surface of a sample. The processor can be in electrical communication with the detector. The memory can store instructions that, when executed by the processor, can cause the processor to perform operations. The operations can include receiving optical data from the detector, determining a polarization change of the reflected light, the polarization change being a function of the optical data, and determining a thickness of the surface layer using the polarization change and the wavelength of the incident light. The optical data can include information regarding the phase difference of the reflected light and the incident light. Also described are other embodiments.Type: ApplicationFiled: December 17, 2015Publication date: June 22, 2017Inventors: Yanmei Song, Yongmei Liu, Deepak Goyal, Donglai David Lu, Marcel A. Wall
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Publication number: 20170170080Abstract: A material thickness adjustment device and associated methods are shown. Material thickness adjustment devices and methods shown include eddy current measurement to determine material thickness during a deposition or removal operation. Feedback from the measured thickness may then be applied to adjust one or more processing parameters to meet a desired thickness.Type: ApplicationFiled: December 14, 2015Publication date: June 15, 2017Applicant: Intel CorporationInventors: Darko Grujicic, Nilanjan Ghosh, Marcel A. Wall, Deepak Goyal