Patents by Inventor Marcel Derevlean

Marcel Derevlean has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Logic cell for programmable gate array
    Patent number: 11671099
    Abstract: A logic cell for a programmable logic integrated circuit apparatus includes a K-input lookup table (LUT) circuit having a primary output Y, wherein Y is any function of K inputs, and at least one additional output (F). A carry circuit receives the outputs of the LUT and a carry-in input CI. The carry circuit generates a sum output S and a carry-out output CO. The carry circuit can be configured to provide S=CI and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and CO=CI if Y=q or to select CO from the set {0, 1, F} if Y?q, where q is a pre-determined value (e.g., such as 0 or 1).
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: June 6, 2023
    Assignee: Microchip Technology Inc.
    Inventors: Jonathan W. Greene, Marcel Derevlean
  • LOGIC CELL FOR PROGRAMMABLE GATE ARRAY
    Publication number: 20220376693
    Abstract: A logic cell for a programmable logic integrated circuit apparatus includes a K-input lookup table (LUT) circuit having a primary output Y, wherein Y is any function of K inputs, and at least one additional output (F). A carry circuit receives the outputs of the LUT and a carry-in input CI. The carry circuit generates a sum output S and a carry-out output CO. The carry circuit can be configured to provide S=CI and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and select CO from the set {0, 1, F}. The carry circuit can alternatively be configured to provide S=EXOR(Y, CI) and CO=CI if Y=q or to select CO from the set {0, 1, F} if Y?q, where q is a pre-determined value (e.g., such as 0 or 1).
    Type: Application
    Filed: November 18, 2021
    Publication date: November 24, 2022
    Applicant: Microchip Technology Inc.
    Inventors: Jonathan W. Greene, Marcel Derevlean
  • Fast carry lookahead circuits
    Patent number: 9170774
    Abstract: A fast lookahead carry adder includes adder logic and lookahead carry-path logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit path, the carry entrance path separate from the carry exit path.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: October 27, 2015
    Assignee: Microsemi SoC Corporation
    Inventors: Volker Hecht, Marcel Derevlean, Jonathan Greene
  • FAST CARRY LOOKAHEAD CIRCUITS
    Publication number: 20120259908
    Abstract: A fast lookahead carry adder includes adder logic and lookahead carry-path logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit path, the carry entrance path separate from the carry exit path.
    Type: Application
    Filed: June 12, 2012
    Publication date: October 11, 2012
    Inventors: Volker Hecht, Marcel Derevlean, Jonathan Greene
  • Fast carry lookahead circuits
    Patent number: 8244791
    Abstract: A fast lookahead carry adder includes adder logic and lookahead carry-path logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit path, the carry entrance path separate from the carry exit path.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: August 14, 2012
    Assignee: Actel Corporation
    Inventors: Volker Hecht, Marcel Derevlean, Jonathan Greene