Abstract: Methods and apparatus are provided for calculating branch metrics, associated with possible transitions between states of a trellis, in a sequence detector for detecting symbol values corresponding to samples of an analog signal transmitted over a channel. For each sample and each transition, the method calculates a plurality of distance values indicative of distance between that sample and respective hypothesized sample values for that transition. In parallel with calculation of the distance values, the sample is compared with a set of thresholds, each defined between a pair of successive hypothesized symbol values arranged in value order, to produce a comparison result. An optimum distance value is selected as a branch metric for the transition in dependence on the comparison result.

Abstract: Methods and apparatus are provided for calculating branch metrics, associated with possible transitions between states of a trellis, in a sequence detector for detecting symbol values corresponding to samples of an analog signal transmitted over a channel. For each sample and each transition, the method calculates a plurality of distance values indicative of distance between that sample and respective hypothesized sample values for that transition. In parallel with calculation of the distance values, the sample is compared with a set of thresholds, each defined between a pair of successive hypothesized symbol values arranged in value order, to produce a comparison result. An optimum distance value is selected as a branch metric for the transition in dependence on the comparison result.

Abstract: A method for timing recovery for a high-speed data transmission system may be provided. The method comprises receiving an analog input signal at an ADC and passing processed digital signal samples to a Viterbi detector. The method also comprises receiving at least one processed signal sample and at least two sets of at least one candidate symbol each from the Viterbi detector and/or the processed signal samples by timing error detectors and forwarding output digital signals of the timing error detectors via loop filters to related multiplexers. Furthermore, the method comprises selecting one digital signal from each of the multiplexers using a select signal generated by the Viterbi detector, and deriving a control signal controlling a sampling clock of the analog-to-digital converter by at least one of the selected digital signals from the multiplexers.

Abstract: Calculating path metrics, associated with respective states of an n-state trellis, by accumulating branch metrics in a sequence detector. Each path metric is represented by N bits plus a wrap-around bit for indicating wrap-around of the N-bit value of that path metric.

Abstract: A multiply and accumulation (MAC) unit for multiplying a provided first and a provided second multiplicand and for adding a provided summand to the resulting product is described. The MAC includes at least one multiplication block which is configured to multiply a first input signal and a second input signal, wherein the first input signal is given in a carry-save adder format and the second input signal is given in a binary format, wherein the multiplication result is provided in a carry-save format, and a carry-save adder which is configured to add to the result of the multiplication the provided summand.

Abstract: The invention relates to a multiply and accumulation (MAC) unit for multiplying a provided first and a provided second multiplicand and for adding a provided summand to the resulting product. The MAC includes at least one multiplication block which is configured to multiply the first multiplicand and the second multiplicand, wherein the first multiplicand is given in a carry-save adder format, wherein the multiplication result is provided in a carry-save format, and a carry-save adder which is configured to add to the result of the multiplication the provided summand.

Abstract: The phase-locked loop according to the invention comprises a frequency acquisition loop. The frequency acquisition loop comprises a counter that is operable to count the number of periods of an oscillator signal occurring during a predetermined period of time that is derived from a reference signal period of a reference signal. The oscillator signal has an oscillator signal frequency and an oscillator signal phase. The frequency acquisition loop also comprises a subtractor that is operable to compare the counted number of periods with a desired division factor, wherein N=fVCOlocked/fref and wherein fVCOlocked denotes a desired frequency of the oscillator signal in a locked state of the phase-locked loop and fref denotes the frequency of said reference signal. The comparison results in a subtractor output frequency value. The phase-locked loop further comprises a phase acquisition loop.

Abstract: A phase locked loop (PLL) which includes a phase frequency detector coupled with a time to digital converter capable of comparing a reference signal with an oscillator signal and generating a digital value representing the phase difference between the reference signal and the oscillator signal. The PLL further includes a state machine for phase acquisition that is capable of generating a control value depending on the digital value, and a controllable oscillator that is capable of generating the oscillator signal depending on the control value.

Abstract: The method for determining jitter of a signal in a serial link according to the invention comprising the following steps: First, a section of the signal transmitted via a transmission channel is sampled at different sampling times. The total number of edges in the section is determined. The neighboring sample values are analyzed and from that a statistical value is formed. From the statistical value and the total number of edges a figure of merit is determined. Finally, by means of a look-up table or a jitter-versus-figure of merit curve, the total jitter corresponding to the figure of merit is derived.