Patents by Inventor Marcel Lugthart
Marcel Lugthart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8289046Abstract: According to one exemplary embodiment, an active termination circuit includes at least one active termination branch, where the at least one active termination branch includes at least one transistor for providing an active termination output. The at least one active termination branch further includes an amplifier driving the at least one transistor, where the amplifier has a non-inverting input coupled to the active termination output via a feedback network. The amplifier controls a current flowing through the at least one transistor so as to provide the active termination output. The active termination output can be provided at a drain of the at least one transistor, where a source of the at least one transistor is coupled to ground through a degeneration transistor and a tail current sink.Type: GrantFiled: June 30, 2011Date of Patent: October 16, 2012Assignee: Broadcom CorporationInventors: Joseph Aziz, Andrew Chen, Derek Tam, Ark-Chew Wong, Agnes Neves Woo, Marcel Lugthart
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Publication number: 20110254584Abstract: According to one exemplary embodiment, an active termination circuit includes at least one active termination branch, where the at least one active termination branch includes at least one transistor for providing an active termination output. The at least one active termination branch further includes an amplifier driving the at least one transistor, where the amplifier has a non-inverting input coupled to the active termination output via a feedback network. The amplifier controls a current flowing through the at least one transistor so as to provide the active termination output. The active termination output can be provided at a drain of the at least one transistor, where a source of the at least one transistor is coupled to ground through a degeneration transistor and a tail current sink.Type: ApplicationFiled: June 30, 2011Publication date: October 20, 2011Applicant: BROADCOM CORPORATIONInventors: Joseph Aziz, Andrew Chen, Derek Tam, Ark-Chew Wong, Agnes Neves Woo, Marcel Lugthart
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Patent number: 7982491Abstract: According to one exemplary embodiment, an active termination circuit includes at least one active termination branch, where the at least one active termination branch includes at least one transistor for providing an active termination output. The at least one active termination branch further includes an amplifier driving the at least one transistor, where the amplifier has a non-inverting input coupled to the active termination output via a feedback network. The amplifier controls a current flowing through the at least one transistor so as to provide the active termination output. The active termination output can be provided at a drain of the at least one transistor, where a source of the at least one transistor is coupled to ground through a degeneration transistor and a tail current sink.Type: GrantFiled: April 8, 2009Date of Patent: July 19, 2011Assignee: Broadcom CorporationInventors: Joseph Aziz, Andrew Chen, Derek Tam, Ark-Chew Wong, Agnes Neves Woo, Marcel Lugthart
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Publication number: 20100259340Abstract: According to one exemplary embodiment, an active termination circuit includes at least one active termination branch, where the at least one active termination branch includes at least one transistor for providing an active termination output. The at least one active termination branch further includes an amplifier driving the at least one transistor, where the amplifier has a non-inverting input coupled to the active termination output via a feedback network. The amplifier controls a current flowing through the at least one transistor so as to provide the active termination output. The active termination output can be provided at a drain of the at least one transistor, where a source of the at least one transistor is coupled to ground through a degeneration transistor and a tail current sink.Type: ApplicationFiled: April 8, 2009Publication date: October 14, 2010Applicant: BROADCOM CORPORATIONInventors: Joseph Aziz, Andrew Chen, Derek Tam, Ark-Chew Wong, Agnes Neves Woo, Marcel Lugthart
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Patent number: 7800449Abstract: Provided is a circuit to perform single-ended to differential conversion while providing common-mode voltage control. The circuit includes a converter to convert a single-ended signal to a differential signal and a stabilizing circuit adapted to receive the differential signal. The stabilizing circuit includes a sensor configured to sense a common-mode voltage level of the differential signal and a comparator having an output port coupled to the converter. The comparator is configured to compare the differential signal common-mode voltage level with a reference signal common-mode voltage level and produce an adjusting signal based upon the comparison. The adjusting signal is applied to the converter via the output port and is operative to adjust a subsequent common-mode voltage level of the differential signal.Type: GrantFiled: February 17, 2005Date of Patent: September 21, 2010Assignee: Qualcomm IncorporatedInventors: Jan Mulder, Marcel Lugthart, Chi-Hung Lin
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Patent number: 7324038Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.Type: GrantFiled: July 24, 2003Date of Patent: January 29, 2008Assignee: Broadcom CorporationInventors: Franciscus Maria Leonardus van der Goes, Jan Mulder, Christopher Michael Ward, Jan Roelof Westra, Ruby van de Plassche, Marcel Lugthart
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Patent number: 7262639Abstract: A differential comparator with improved bit-error rate performance operating with a low supply voltage. The differential comparator includes a first pair of transistors receiving a differential input. A second pair of transistors is coupled to the first pair of transistors. A pair of resistive elements is connected between the first pair and second pair of transistors so as to increase bias currents shared by the first and second pairs of transistors. The increased bias currents reduce a time required by the differential comparator to transition from a meta-stable state to a stable state, thereby improving a bit-error rate of the differential comparator. The resistive elements can use linear resistors or transmission gates. Gates of either the first or second pair of transistors can provide an output.Type: GrantFiled: January 21, 2005Date of Patent: August 28, 2007Assignee: Broadcom CorporationInventors: Jan Mulder, Franciscus Maria Leonardus van der Goes, Marcel Lugthart
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Publication number: 20060164126Abstract: A differential comparator with improved bit-error rate performance operating with a low supply voltage. The differential comparator includes a first pair of transistors receiving a differential input. A second pair of transistors is coupled to the first pair of transistors. A pair of resistive elements is connected between the first pair and second pair of transistors so as to increase bias currents shared by the first and second pairs of transistors. The increased bias currents reduce a time required by the differential comparator to transition from a meta-stable state to a stable state, thereby improving a bit-error rate of the differential comparator. The resistive elements can use linear resistors or transmission gates. Gates of either the first or second pair of transistors can provide an output.Type: ApplicationFiled: January 21, 2005Publication date: July 27, 2006Inventors: Jan Mulder, Franciscus van der Goes, Marcel Lugthart
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Publication number: 20050140446Abstract: Provided is a circuit to perform single-ended to differential conversion while providing common-mode voltage control. The circuit includes a converter to convert a single-ended signal to a differential signal and a stabilizing circuit adapted to receive the differential signal. The stabilizing circuit includes a sensor configured to sense a common-mode voltage level of the differential signal and a comparator having an output port coupled to the converter. The comparator is configured to compare the differential signal common-mode voltage level with a reference signal common-mode voltage level and produce an adjusting signal based upon the comparison. The adjusting signal is applied to the converter via the output port and is operative to adjust a subsequent common-mode voltage level of the differential signal.Type: ApplicationFiled: February 17, 2005Publication date: June 30, 2005Applicant: Broadcom CorporationInventors: Jan Mulder, Marcel Lugthart, Chi-Hung Lin
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Patent number: 6873210Abstract: Provided is a circuit to perform single-ended to differential conversion while providing common-mode voltage control. The circuit includes a converter to convert a single-ended signal to a differential signal and a stabilizing circuit adapted to receive the differential signal. The stabilizing circuit includes a sensor configured to sense a common-mode voltage level of the differential signal and a comparator having an output port coupled to the converter. The comparator is configured to compare the differential signal common-mode voltage level with a reference signal common-mode voltage level and produce an adjusting signal based upon the comparison. The adjusting signal is applied to the converter via the output port and is operative to adjust a subsequent common-mode voltage level of the differential signal.Type: GrantFiled: March 4, 2004Date of Patent: March 29, 2005Assignee: Broadcom CorporationInventors: Jan Mulder, Marcel Lugthart, Chi-Hung Lin
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Publication number: 20040164770Abstract: Provided is a circuit to perform single-ended to differential conversion while providing common-mode voltage control. The circuit includes a converter to convert a single-ended signal to a differential signal and a stabilizing circuit adapted to receive the differential signal. The stabilizing circuit includes a sensor configured to sense a common-mode voltage level of the differential signal and a comparator having an output port coupled to the converter. The comparator is configured to compare the differential signal common-mode voltage level with a reference signal common-mode voltage level and produce an adjusting signal based upon the comparison. The adjusting signal is applied to the converter via the output port and is operative to adjust a subsequent common-mode voltage level of the differential signal.Type: ApplicationFiled: March 4, 2004Publication date: August 26, 2004Applicant: Broadcom CorporationInventors: Jan Mulder, Marcel Lugthart, Chi-Hung Lin
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Publication number: 20040155807Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output ofthe coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.Type: ApplicationFiled: July 24, 2003Publication date: August 12, 2004Applicant: Broadcom CorporationInventors: Franciscus Maria Leonardus van der Goes, Jan Mulder, Christopher Michael Ward, Jan Roelof Westra, Rudy van de Plassche, Marcel Lugthart
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Patent number: 6771127Abstract: Provided is a circuit to perform single-ended to differential conversion while providing common-mode voltage control. The circuit includes a converter to convert a single-ended signal to a differential signal and a stabilizing circuit adapted to receive the differential signal. The stabilizing circuit includes a sensor configured to sense a common-mode voltage level of the differential signal and a comparator having an output port coupled to the converter. The comparator is configured to compare the differential signal common-mode voltage level with a reference signal common-mode voltage level and produce an adjusting signal based upon the comparison. The adjusting signal is applied to the converter via the output port and is operative to adjust a subsequent common-mode voltage level of the differential signal.Type: GrantFiled: March 26, 2002Date of Patent: August 3, 2004Assignee: Broadcom CorporationInventors: Jan Mulder, Marcel Lugthart, Chi-Hung Lin
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Patent number: 6727756Abstract: Provided is a circuit to perform single-ended to differential conversion while providing common-mode voltage control. The circuit includes a converter to convert a single-ended signal to a differential signal and a stabilizing circuit adapted to receive the differential signal. The stabilizing circuit includes a sensor configured to sense a common-mode voltage level of the differential signal and a comparator having an output port coupled to the converter. The comparator is configured to compare the differential signal common-mode voltage level with a reference signal common-mode voltage level and produce an adjusting signal based upon the comparison. The adjusting signal is applied to the converter via the output port and is operative to adjust a subsequent common-mode voltage level of the differential signal.Type: GrantFiled: April 30, 2003Date of Patent: April 27, 2004Assignee: Broadcom CorporationInventors: Jan Mulder, Marcel Lugthart, Chi-Hung Lin
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Publication number: 20030218556Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.Type: ApplicationFiled: February 6, 2003Publication date: November 27, 2003Applicant: Broadcom CorporationInventors: Franciscus Maria Leonardus van der Goes, Jan Mulder, Christopher Michael Ward, Jan Roelof Westra, Rudy van de Plassche, Marcel Lugthart
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Patent number: 6653966Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.Type: GrantFiled: February 6, 2003Date of Patent: November 25, 2003Assignee: Broadcom CorporationInventors: Franciscus Maria Leonardus van der Goes, Jan Mulder, Christopher Michael Ward, Jan Roelof Westra, Rudy van de Plassche, Marcel Lugthart
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Publication number: 20030197561Abstract: Provided is a circuit to perform single-ended to differential conversion while providing common-mode voltage control. The circuit includes a converter to convert a single-ended signal to a differential signal and a stabilizing circuit adapted to receive the differential signal. The stabilizing circuit includes a sensor configured to sense a common-mode voltage level of the differential signal and a comparator having an output port coupled to the converter. The comparator is configured to compare the differential signal common-mode voltage level with a reference signal common-mode voltage level and produce an adjusting signal based upon the comparison. The adjusting signal is applied to the converter via the output port and is operative to adjust a subsequent common-mode voltage level of the differential signal.Type: ApplicationFiled: April 30, 2003Publication date: October 23, 2003Inventors: Jan Mulder, Marcel Lugthart, Chi-Hung Lin
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Publication number: 20030184380Abstract: Provided is a circuit to perform single-ended to differential conversion while providing common-mode voltage control. The circuit includes a converter to convert a single-ended signal to a differential signal and a stabilizing circuit adapted to receive the differential signal. The stabilizing circuit includes a sensor configured to sense a common-mode voltage level of the differential signal and a comparator having an output port coupled to the converter. The comparator is configured to compare the differential signal common-mode voltage level with a reference signal common-mode voltage level and produce an adjusting signal based upon the comparison. The adjusting signal is applied to the converter via the output port and is operative to adjust a subsequent common-mode voltage level of the differential signal.Type: ApplicationFiled: March 26, 2002Publication date: October 2, 2003Applicant: Broadcom IncorporatedInventors: Jan Mulder, Marcel Lugthart, Chi-Hung Lin
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Patent number: 6583747Abstract: An N-bit analog to digital converter includes a reference ladder, a track-and-hold amplifier connected to an input voltage, a coarse ADC amplifier connected to a coarse capacitor at its input and having a coarse ADC reset switch controlled by a first clock phase of a two-phase clock, a fine ADC amplifier connected to a fine capacitor at its input and having a fine ADC reset switch controlled by a second clock phase of the two-phase clock, a switch matrix that selects a voltage subrange from the reference ladder for use by the fine ADC amplifier based on an output of the coarse ADC amplifier, and wherein the coarse capacitor is charged to a coarse reference ladder voltage during the first clock phase and connected to the T/H output during the second clock phase, wherein the fine capacitor is connected to a voltage subrange during the first clock phase and to the T/H output during the second clock phase, and an encoder that converts outputs of the coarse and fine ADC amplifiers to an N-bit output.Type: GrantFiled: May 31, 2002Date of Patent: June 24, 2003Assignee: Broadcom CorporationInventors: Franciscus Maria Leonardus van der Goes, Jan Mulder, Christopher Michael Ward, Jan Roelof Westra, Rudy van de Plassche, Marcel Lugthart