Patents by Inventor Marcel ter Beek

Marcel ter Beek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Low voltage complement ESD protection structures
    Patent number: 6690069
    Abstract: In an ESD protection device using a SCR-like structure, a vertical device is provided that is highly robust and easily allows the triggering voltage to be adjusted during manufacture. Furthermore it is implementable in complementary form based on PNP and NPN BJT structures, to provide both positive and negative pulse protection.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: February 10, 2004
    Assignee: National Semiconductor Corp
    Inventors: Vladislav Vashchenko, Ann Concannon, Peter J. Hopper, Marcel ter Beek
  • Stand-alone triggering structure for ESD protection of high voltage CMOS
    Patent number: 6660602
    Abstract: In a stand-alone snapback NMOS ESD protection structure method of manufacturing, the breakdown voltage is reduced and the structure is made more resilient to hot carrier and soft leakage degradation in the gate region by blocking the NLDD and partially blocking the n+ drain region between the gate and drain region.
    Type: Grant
    Filed: March 12, 2002
    Date of Patent: December 9, 2003
    Assignee: National Semiconductor Corp.
    Inventors: Vladislav Vashchenko, Ann Concannon, Peter J. Hopper, Marcel ter Beek