Patents by Inventor Marcel Van De Gevel

Marcel Van De Gevel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240171154
    Abstract: A low-pass filter circuit comprising: a low-pass filter input terminal; a low-pass filter output terminal; a reference terminal; at least three filter resistors connected in series with each other between the low-pass filter input terminal and the low-pass filter output terminal, such that there is a resistor-connecting-node between each adjacent pair of filter resistors; a plurality of filter capacitors, one for each of the resistor-connecting-nodes, wherein each of the filter capacitors is connected between an associated resistor-connecting-node and the reference terminal; and a branch connected in parallel with the at least three filter resistors, wherein the branch comprises a bridging capacitor and a bridging resistor in series with each other.
    Type: Application
    Filed: October 23, 2023
    Publication date: May 23, 2024
    Inventors: Marcel van de Gevel, Federico Bruccoleri, Mark Stoopman, Koen van Hartingsveldt
  • Patent number: 10003343
    Abstract: A phase locked loop circuit comprising: a phase detector configured to compare the phase of an input signal with the phase of a feedback signal in order to provide an up-phase signal and a down-phase-signal; an oscillator-driver configured to: apply an up-weighting-value to the up-phase signal in order to provide a weighted-up-phase signal; apply a down-weighting-value to the down-phase signal in order to provide a weighted-down-phase signal; and combine the weighted-up-phase signal with the weighted-down-phase signal in order to provide an oscillator-driver-output-signal; and a controller configured to: set the up-weighting-value and the down-phase-weighting as a first-set-of-unequal-weighting-values, and replace the first-set-of-unequal-weighting-values with a second-set-of-unequal-weighting-values if an operating signal of the phase locked loop circuit reaches a limit-value without satisfying a threshold value.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: June 19, 2018
    Assignee: NXP B.V.
    Inventors: Kaveh Kianush, Evert-Jan Pol, Marcel Van De Gevel
  • Publication number: 20170214407
    Abstract: A phase locked loop circuit comprising: a phase detector configured to compare the phase of an input signal with the phase of a feedback signal in order to provide an up-phase signal and a down-phase-signal; an oscillator-driver configured to: apply an up-weighting-value to the up-phase signal in order to provide a weighted-up-phase signal; apply a down-weighting-value to the down-phase signal in order to provide a weighted-down-phase signal; and combine the weighted-up-phase signal with the weighted-down-phase signal in order to provide an oscillator-driver-output-signal; and a controller configured to: set the up-weighting-value and the down-phase-weighting as a first-set-of-unequal-weighting-values, and replace the first-set-of-unequal-weighting-values with a second-set-of-unequal-weighting-values if an operating signal of the phase locked loop circuit reaches a limit-value without satisfying a threshold value.
    Type: Application
    Filed: January 11, 2017
    Publication date: July 27, 2017
    Inventors: Kaveh Kianush, Evert-Jan Pol, Marcel VAN DE Gevel
  • Publication number: 20060181361
    Abstract: The present invention relates to a crystal oscillator for generating an oscillator signal having a predetermined frequency, wherein a frequency-dependent negative resistance circuit (FDNR) having a negative resistance inversely proportional to frequency squared is connected to an oscillator crystal (Q). Thereby, the voltage across the crystal (Q) approaches the time integral of a current supplied by an amplitude control means (10) and the input voltage of the amplitude control means (10) approaches the time integral of the current flowing through the crystal (Q). Due to this integration behavior of the frequency-dependent negative resistance circuit (FDNR), no accurate capacitors or other accurate reactive components are necessary.
    Type: Application
    Filed: July 16, 2004
    Publication date: August 17, 2006
    Inventors: Marcel Van De Gevel, Onno Kuijken