Patents by Inventor Marcel Van der Goot
Marcel Van der Goot has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230409201Abstract: A conflict-free parallel radix sorting algorithm, and devices and systems implementing this algorithm, schedules memory copies of data elements of a large dataset so that there is always a single copy to each target memory each cycle of operation for the system implementing the algorithm. The conflict-free parallel radix sorting algorithm eliminates memory copying conflicts in copying data elements from different source memories to the same target memory and in this way maintains maximum throughput for the copying of data elements from source memories to target memories, reducing the time required to sort the data elements of the large dataset.Type: ApplicationFiled: January 13, 2023Publication date: December 21, 2023Inventors: Marcel Van der Goot, Raymond Nijssen, Christopher C. LaFrieda
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Publication number: 20230325334Abstract: A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.Type: ApplicationFiled: June 13, 2023Publication date: October 12, 2023Inventors: Daniel Pugh, Raymond Nijssen, Michael Philip Fitton, Marcel Van der Goot
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Patent number: 11734216Abstract: A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.Type: GrantFiled: February 18, 2022Date of Patent: August 22, 2023Assignee: Achronix Semiconductor CorporationInventors: Daniel Pugh, Raymond Nijssen, Michael Philip Fitton, Marcel Van der Goot
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Publication number: 20230244446Abstract: A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.Type: ApplicationFiled: March 23, 2023Publication date: August 3, 2023Inventors: Daniel Pugh, Raymond Nijssen, Michael Philip Fitton, Marcel Van der Goot
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Patent number: 11650792Abstract: A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.Type: GrantFiled: January 6, 2022Date of Patent: May 16, 2023Assignee: Achronix Semiconductor CorporationInventors: Daniel Pugh, Raymond Nijssen, Michael Philip Fitton, Marcel Van der Goot
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Publication number: 20220214990Abstract: A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.Type: ApplicationFiled: February 18, 2022Publication date: July 7, 2022Inventors: Daniel Pugh, Raymond Nijssen, Michael Philip Fitton, Marcel Van der Goot
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Publication number: 20220129244Abstract: A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.Type: ApplicationFiled: January 6, 2022Publication date: April 28, 2022Inventors: Daniel Pugh, Raymond Nijssen, Michael Philip Fitton, Marcel Van der Goot
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Patent number: 11288220Abstract: A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.Type: GrantFiled: October 18, 2019Date of Patent: March 29, 2022Assignee: Achronix Semiconductor CorporationInventors: Daniel Pugh, Raymond Nijssen, Michael Philip Fitton, Marcel Van der Goot
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Patent number: 11256476Abstract: A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.Type: GrantFiled: August 8, 2019Date of Patent: February 22, 2022Assignee: Achronix Semiconductor CorporationInventors: Daniel Pugh, Raymond Nijssen, Michael Philip Fitton, Marcel Van der Goot
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Publication number: 20210117356Abstract: A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.Type: ApplicationFiled: October 18, 2019Publication date: April 22, 2021Inventors: Daniel Pugh, Raymond Nijssen, Michael Philip Fitton, Marcel Van der Goot
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Publication number: 20210042087Abstract: A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.Type: ApplicationFiled: August 8, 2019Publication date: February 11, 2021Inventors: Daniel Pugh, Raymond Nijssen, Michael Philip Fitton, Marcel Van der Goot
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Patent number: 8661378Abstract: Methods, systems, and circuits that implement timing analyses of an asynchronous system are described. A method may include converting a synchronous circuit design into an asynchronous representation, wherein a critical path may be identified. The critical path may be converted to a corresponding path in the synchronous circuit design. Additional methods, systems, and circuits are disclosed.Type: GrantFiled: September 30, 2009Date of Patent: February 25, 2014Assignee: Achronix Semiconductor CorporationInventors: Rajit Manohar, Gael Paul, Raymond Nijssen, Marcel Van der Goot, Clinton W. Kelly, Virantha Ekanayake
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Patent number: 8301933Abstract: Methods, systems, and circuits for implementing multi-clock designs in asynchronous logic circuits are described. A method may include associating one or more data tokens with a clock domain of a multi-clock domain netlist. A durational relationship between a clock period associated with the clock domain and one or more other clock domains of the multi-clock domain netlist may be determined. Data tokens used in other clock domains may be transformed based on the determined relationship.Type: GrantFiled: September 14, 2009Date of Patent: October 30, 2012Assignee: Achronix Semiconductor CorporationInventors: Rajit Manohar, Clinton W. Kelly, Virantha Ekanayake, Gael Paul, Raymond Nijssen, Marcel Van der Goot
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Patent number: 8234607Abstract: A synchronous circuit design is converted to an asynchronous circuit by converting synchronous circuit logic to an asynchronous circuit logic, and one or more additional tokens into the converted asynchronous circuit. The circuit is initialized with a desired additional number of tokens placed in the asynchronous circuit, or a desired number of tokens are inserted at an input before taking tokens from an output.Type: GrantFiled: September 15, 2009Date of Patent: July 31, 2012Assignee: Achronix Semiconductor CorporationInventors: Virantha Ekanayake, Clinton W. Kelly, Rajit Manohar, Christopher LaFrieda, Gael Paul, Raymond Nijssen, Marcel Van der Goot
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Patent number: 8078899Abstract: Apparatus, systems, and methods operate to receive a sufficient number of asynchronous input tokens at the inputs of an asynchronous apparatus to conduct a specified processing operation, some of the tokens decoded to determine an operation type associated with the specified processing operation; to receive an indication that outputs of the asynchronous apparatus are ready to conduct the specified processing operation; to signal a synchronous circuit to process data included in the tokens according to the specified processing operation; and to convert synchronous outputs from the synchronous circuit into asynchronous output tokens to be provided to outputs of the asynchronous apparatus when the synchronous outputs result from the specified processing operation. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: February 8, 2011Date of Patent: December 13, 2011Assignee: Achronix Semiconductor CorporationInventors: Rajit Manohar, Clinton W. Kelly, Virantha Ekanayake, Christopher LaFrieda, Hong Tam, Ilya Ganusov, Raymond Nijssen, Marcel Van der Goot
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Patent number: 7982502Abstract: A synchronous circuit design is converted to an asynchronous circuit by converting synchronous circuit logic to an asynchronous circuit logic, and converting one or more asynchronous inputs at a circuit boundary to an asynchronous input to the converted asynchronous circuit logic, such that the converted asynchronous input is operable to generate a token upon observing a change in state on the asynchronous input. One or more asynchronous outputs at a circuit boundary is converted to an asynchronous output from the converted asynchronous circuit logic, such that the converted asynchronous output is operable to output updated data as soon as changed data is received from the converted asynchronous circuit logic in the asynchronous output.Type: GrantFiled: September 15, 2009Date of Patent: July 19, 2011Assignee: Achronix Semiconductor CorporationInventors: Rajit Manohar, Gael Paul, Marcel Van der Goot, Raymond Nijssen, Christopher LaFrieda, Clinton W. Kelly, Virantha Ekanayake
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Publication number: 20110130171Abstract: Apparatus, systems, and methods operate to receive a sufficient number of asynchronous input tokens at the inputs of an asynchronous apparatus to conduct a specified processing operation, some of the tokens decoded to determine an operation type associated with the specified processing operation; to receive an indication that outputs of the asynchronous apparatus are ready to conduct the specified processing operation; to signal a synchronous circuit to process data included in the tokens according to the specified processing operation; and to convert synchronous outputs from the synchronous circuit into asynchronous output tokens to be provided to outputs of the asynchronous apparatus when the synchronous outputs result from the specified processing operation. Additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: February 8, 2011Publication date: June 2, 2011Inventors: Rajit Manohar, Clinton W. Kelly, Virantha Ekanayake, Christopher LaFrieda, Hong Tam, Ilya Ganusov, Raymond Nijssen, Marcel Van der Goot
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Publication number: 20110078644Abstract: Methods, systems, and circuits that implement timing analyses of an asynchronous system are described. A method may include converting a synchronous circuit design into an asynchronous representation, wherein a critical path may be identified. The critical path may be converted to a corresponding path in the synchronous circuit design. Additional methods, systems, and circuits are disclosed.Type: ApplicationFiled: September 30, 2009Publication date: March 31, 2011Inventors: Rajit Manohar, Gael Paul, Raymond Nijssen, Marcel Van der Goot, Clinton W. Kelly, Virantha Ekanayake
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Publication number: 20110062987Abstract: Apparatus, systems, and methods operate to receive a sufficient number of asynchronous input tokens at the inputs of an asynchronous apparatus to conduct a specified processing operation, some of the tokens decoded to determine an operation type associated with the specified processing operation; to receive an indication that outputs of the asynchronous apparatus are ready to conduct the specified processing operation; to signal a synchronous circuit to process data included in the tokens according to the specified processing operation; and to convert synchronous outputs from the synchronous circuit into asynchronous output tokens to be provided to outputs of the asynchronous apparatus when the synchronous outputs result from the specified processing operation. Additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: September 14, 2009Publication date: March 17, 2011Inventors: Rajit Manohar, Clinton W. Kelly, Virantha Ekanayake, Christopher LaFrieda, Hong Tam, Ilya Ganusov, Raymond Nijssen, Marcel Van der Goot
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Publication number: 20110062991Abstract: A synchronous circuit design is converted to an asynchronous circuit by converting synchronous circuit logic to an asynchronous circuit logic, and converting one or more asynchronous inputs at a circuit boundary to an asynchronous input to the converted asynchronous circuit logic, such that the converted asynchronous input is operable to generate a token upon observing a change in state on the asynchronous input. One or more asynchronous outputs at a circuit boundary is converted to an asynchronous output from the converted asynchronous circuit logic, such that the converted asynchronous output is operable to output updated data as soon as changed data is received from the converted asynchronous circuit logic in the asynchronous output.Type: ApplicationFiled: September 15, 2009Publication date: March 17, 2011Inventors: Rajit Manohar, Gael Paul, Marcel Van der Goot, Raymond Nijssen, Christopher LaFrieda, Clinton W. Kelly, Virantha Ekanayake