Abstract: A method for producing a layer covering the first surfaces of a structure and leaving the second surfaces uncovered including a sequence for forming an initial layer by PEALD deposition, the sequence including cycles, each including injections of first and second precursor in a reaction chamber, and plasma formation in the reaction chamber. The cycles are carried out at a temperature Tcycle such that Tcycle ? (Tmin - 20° C.), Tmin being the minimum temperature of a nominal temperature window for a PEALD deposition. The method includes exposing the initial layer to a densification plasma such that the exposure to the ion flow makes the material on the first surfaces more resistant to etching than the material on the second surfaces. The method also includes a selective etching step, such that the initial layer covers the first surfaces of the front face of the structure by leaving the second surfaces uncovered.

Abstract: A method for forming spacers on a gate pattern includes deposition of a first dielectric layer having basal portions on an active layer and side portions of the edges of the pattern; anisotropic modification of only the basal portions of the first layer, so as to obtain modified basal portions; deposition of a second dielectric layer on the first layer, also having basal and side portions; anisotropic etching of only the basal portions of the second layer, so as to remove these basal portions while conserving the side portions; and removal of the modified basal portions while conserving the first and second non-modified side portions, by selective etching of the modified dielectric material vis-à-vis the non-modified dielectric material.

Abstract: A method for forming spacers on a gate pattern includes deposition of a first dielectric layer having basal portions on an active layer and side portions of the edges of the pattern; anisotropic modification of only the basal portions of the first layer, so as to obtain modified basal portions; deposition of a second dielectric layer on the first layer, also having basal and side portions; anisotropic etching of only the basal portions of the second layer, so as to remove these basal portions while conserving the side portions; and removal of the modified basal portions while conserving the first and second non-modified side portions, by selective etching of the modified dielectric material vis-à-vis the non-modified dielectric material.

Abstract: The invention relates to a process for making a gate for a CMOS transistor structure, made from a stack realized on a face in a semi-conducting material of a substrate, said stack comprising a gate isolation layer, a gate material layer and a gate mask in sequence, the process comprising the following steps: a) anisotropic etching of the top part of the gate material layer not masked by the gate mask, this etching step leaving the bottom part of the gate material layer and leading to the formation of a deposit composed of etching products on the etching sides resulting from the anisotropic etching, b) treatment of the deposit composed of etching products, to make a protection layer reinforced against subsequent etching of the gate material, c) etching of the bottom part of the gate material layer as far as the gate isolation layer, this etching comprising isotropic etching of the gate material layer to make the gate shorter at the bottom than at the top.

Abstract: The invention relates to a process for making a gate for a CMOS transistor structure, made from a stack realized on a face in a semi-conducting material of a substrate, said stack comprising a gate isolation layer, a gate material layer and a gate mask in sequence, the process comprising the following steps: