Abstract: A serial communication system transfers respective first and second signals via respective parallel signal carriers from a transmitter circuit to a receiver circuit. In synchronization with a clock signal (150), the transmitter circuit (110) serially represents a combination of the clock signal and data bit(s) (160) of a data message as the first and second signals (130, 140). At a data bit boundary, the transmitter circuit effects a transition of the first signal (130) if the data bit to be transmitted has a first value and effects a transition of the second signal (140) if the data bit has a different second value. The receiver circuit (120) recovers the clock signal by detecting and combining signal transitions of the first and second signal, for instance using an XOR function, and recovers the data message from the first and/or the second signal.

Abstract: A non-volatile, random access memory cell comprises first and second inverters each having an output node cross-coupled by cross-coupling means to an input node of the other inverter for forming a MOS RAM cell. The output node of each inverter is selectively connected via the conductor paths of separate access transistors to respective bit lines. The control electrodes of the access transistors are connected to a common word line. In particular, both RAM and programmable Read-Only operation of said memory cell are provided. Thereto, the cross-coupling comprises capacitors (C1, C2) each in series with a control electrode of a respective p-type transistor of the first and second inverters. This renders both interconnecting nodes between a capacitor and the gate electrode of its associated p-channel transistor floating. Isolators around these nodes render the cell data-retentive. The nodes are transiently and electrically programmable through signals on the bit and word lines of the cell.

Abstract: A magnetic field sensor has a substrate on which a plurality of resistive elements form a double Wheatstone bridge circuit, at least one of the resistive elements in each bridge having a magneto-resistive characteristic. The two bridges are identical except in that, if a given magneto-resistive element in a given branch in one bridge has a positive output polarity, then the corresponding magneto-resistive element in the same branch in the other bridge will have a negative output polarity. By adding the output signals of the two Wheatstone bridges a zero-point offset of the sensor can be determined and eliminated. There is no need to employ the so-called flipping technique employed for that purpose in conventional sensors, which requires increased power consumption.

Abstract: In a method of demodulating an analog chrominance signal (C), digital quadrature signals are generated (DPA, SIN ROM, COS ROM) for demodulating (MUL DAC U, MUL DAC V) the analog chrominance signal (C) to obtain analog demodulated color difference signals (U, V). A digital phase error signal is furnished (.SIGMA..DELTA.mod) from at least one (V) of the analog demodulated color difference signals (U, V). The digital phase error signal is digitally filtered (DLF) to obtain a phase control signal (K) for the digital quadrature signals generation (DPA, SIN ROM, COS ROM).

Abstract: In a digital filter in which coefficients are realised using power of two weighting factors, it can occur that due to rounding errors the output signal shows some inaccuracies. By decomposing the filter coefficients into powers of two in such a way that most powers of two have a counterpart with an opposite sign, the rounding errors tend to cancel, resulting in a more accurate filter.

Abstract: A sub-ranging analog-to-digital converter includes, in cascade, a coarse converter, a digital-to-analog converter, a subtracter circuit and a fine converter. Errors of the coarse converter are detected in the fine converter by means of an overflow detector and an underflow detector which generate an overflow signal (OF) and an underflow signal (UF), respectively. The digital output (D.sub.A) of the coarse converter is corrected by first subtracting one LBS in a decoder and then, in response to the overflow and underflow signal, adding thereto zero, one or two LBSs.

Abstract: A clocked comparator circuit comprises an input stage and a sample-and-hold circuit and an amplifier-latch circuit coupled to the output of the input stage. The sample-and-hold circuit provides an accurate offset-voltage compensation and the amplifier-latch circuit provides a high operating speed by means of a switchable current source (S6, T11). Switches are provided so that the amplifier-latch circuit constitutes a differential load having a high positive impedance during a first state of a clock signal, a low positive impedance during a next state of the clock signal, and a negative impedance during a following state of the clock signal.

Abstract: A sample-and-hold device provided with a series arrangement of a first and a second integrating circuit, each including an input, an output and a control signal input. The output of the first integrating circuit is coupled to the input of the second integrating circuit. A control unit supplies a first and a second control signal to the control signal inputs of the first and the second integrating circuit, respectively. The output of the second integrating circuit is fed back to the input of the first integrating circuit. The first integrating circuit is controlled by the first control signal in a manner such that in the first integrating circuit an integration step is performed upon the difference between the input voltage on the input of the first integrating circuit and the output voltage fed back from the output of the second integrating circuit.

Abstract: Digital-to-analog converter having a reference voltage divider and a selection circuit by which the voltage at one of the nodal points of the reference voltage divider can be switched-through to the output of the converter. The selection circuit is controlled by selection signals coming from a decoder circuit by which the digital input signal is decoded. In addition, the converter includes a bias voltage divider which can apply different bias voltages to a level shifting circuit by which the signal level of the selection signals can be shifted.

Abstract: The invention relates to a semiconductor device including a charge transfer device having an output stage (8). The output stage (8) has a read-out zone (9), a feedback capacitor (11) and an amplifier (10). An inverting input (15) of the amplifier (10) is connected to the read-out zone (9) and an output (16) of the amplifier (10) is fed back via the feedback capacitor (11) to the inverting input (15). According to the invention, the capacitor (11) is a capacitor of the MOS type and means are provided by which during operation of the charge transfer device the surface potential of a surface region (13) in the capacitor (11) is solely determined by the potential of the read-out zone (9). Consequently, the capacitance of the feedback capacitor (11) is dependent upon the potential across it, as a result of which there is a linear relation between the charge supplied to the read-out zone (9) and the voltage variation across the capacitor (11 ).

Abstract: A digital-to-analog converter for converting a digital signal having a word length n into an analog signal comprises a series arrangement of at least two integrating circuits (1,2) and a control unit (18) for supplying a first and a second control signal (S1, S2) to the first and the second integrating circuit. The integrating circuits are adapted to perform an integration step under the influence of the first and the second control signal. The control unit is adapted to generate, in this order, the first control signal M1 times, the second control signal M2 times, the first control signal M3 times and the second control signal M4 times. For converting arbitrary digital signals M2+M4 is equal to a constant (k). Due to this measure an offset voltage which is independent of the value of the n-bit digital signal to be converted is produced at the output (8) of the converter. For converting n-bit digital signal the constant k is preferably taken to be equal to 2.sup.p in which p.ltoreq.n.

Abstract: A digital-to-analog converter for converting a digital signal having a word length n into an analog signal. The converter includes at least two switched capacitor integrators (1, 2) arranged in series and a control unit (18) for applying control signals to the integrators which perform an integration step under the influence of the control signal. Each integrator is provided with a capacitor network (11, 12) having at least two capacitors (27.1, 27.2, . . . ; 28.1, 28.2, . . . ) coupled between the input (13; 4) of the integrator and the inverting input (-) of an associated amplifier stage (5; 6). A capacitor (9; 10) is coupled between the inverting input (-) and the output (7; 8) of this amplifier stage. The control unit is adapted to apply, in this order, a first control signal to the first integrator (1), a second control signal to the second integrator (2), a third control signal to the first integrator and a fourth control signal to the second integrator.

Abstract: The invention relates to a charge-coupled image sensor of the line transfer type comprising a number of parallel lines (2-6) which are each constituted by an n-phase CCD. An electrode (12-16) of each CCD is arranged parallel to this CCD separately for each CCD. The other (n-1) electrodes (17-20) extend transversely to the charge transport direction over all CCD's. The first-mentioned electrode (12-16) is used as a selection gate and is moreover used, depending upon the applied voltage, as an integration gate or as a blocking gate during the integration period.

Abstract: The invention relates to a CCD having a diode cut-off input, a reference voltage being applied to the input diode and the input signal being supplied to an input gate located in front of the first clock electrode. If the electrodes are composed of a transfer part and a storage part with an incorporated potential difference, it is possible that incomplete charge transport may occur from the input to the first clock electrode. In order to avoid this incomplete charge transport and/or to be able to enlarge the dynamic range of the input signal, a larger clock voltage, for example 10 V, is applied to the first clock electrode than to the following clock electrodes, which receive, for example, 5 V. In a preferred embodiment, the 5 V clock voltage can be supplied for this purpose by a boots-trap circuit ot the first clock electrode.

Abstract: The invention relates to a CCD having a so-called diode cut-off input, in which the input diode is applied to a reference voltage and the input signal is supplied to the input gate located in front of the first clock electrode. More particularly, if the electrodes are composed of a transfer part and a storage part with an incorporated potential difference, it is possible that, when charge is transported from the input gate to the first clock electrode, a large amount of charge is left behind. In order to avoid this and/or to be able to enlarge the dynamic range of the input signal, a MOST switch controlled by the same clock voltage as the first clock electrode is arranged between the input gate and a reference voltage, for example ground. This switch becomes conducting when the charge is transferred, as a result of which the potential level below the input gate can be adjusted above the surface potential below the transfer part of the first clock electrode.

Abstract: A photodetector for use in an angular displacement measuring apparatus consists a multiple photocell consisting of radially extending strip-shaped photodiodes (11 to 15). According to the invention, the diodes are connected alternately via switching electrodes (7) to an output electrode (6), which is constituted by a conductive image-defining shield arranged above the switching electrodes and comprises two opposite bands (AB, CD), whose widths (b.sub.1, b.sub.2) are substantially inversely proportional to their radii of curvature in order to reduce trouble by cross-talk. The photodetector may be an integrated circuit, which comprises besides the multiple photocell also a part of the processing circuit. The invention also relates to an apparatus for measuring angular displacements by means of such a photodetector.

Abstract: A method of detecting binary information from the pulse-shaped output signal of a CCD uses a varying reference voltage which depends on the amplitude of the last pulse detected, in order to render the detection system immune to pulse distortion as a result of transfer losses in the CCD.

Abstract: An image enhancement circuit for eliminating noise from a series of image signals g.sub.i (t) representing images of a quasi-stationary object in a noisy environment. The image enhancement circuit is provided with an accumulator circuit and a weighting circuit. The weighting circuit receives a difference signal indicating the difference between the actual image signal g.sub.i (n) and the output signal h.sub.i (n) of the accumulator circuit. In the weighting circuit, the difference signal is multiplied by a weighting factor k(i) which is dependent on the ordinal number i of the actual image signal g.sub.i (n). For example, k(i)=1/i. The weighted difference signal is then added to the accumulator.

Abstract: The invention relates to a charge detector, more particularly for reading binary information in a CTD. The detector includes a flipflop having two cross-coupled MOS transistors and two MOS transistors acting as loads. The signal to be read and the reference signal are supplied to the gates of the loads. The junctions between the driver transistors and the loads are connected to reset transistors. The drains of the loads are applied to a (fixed) supply voltage and the sources of the driver transistors are applied via a switching transistor to the supply voltage return. The circuit arrangement is operated so that before the activation of the flipflop the said junctions are set to a signal-dependent preadjustment. When the switching transistor is then energized, the flipflop will be in the correct stage with a higher degree of reliability and without being influenced by clock cross-talk.

Abstract: One or more defective elements regularly occur in series-parallel-series digital units comprising several elements. The described system offers a solution for the construction of a series-parallel-series digital system by means of a number of series-parallel-series digital units comprising one or more defective elements; in this system only a part of the data stream passing through the system appears as being unreliable on the output thereof. Moreover, said unreliable part will always be situated within the same serial data stream, while the other serial data stream on the output will not be affected thereby.