Patents by Inventor Marcello Coppola
Marcello Coppola has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11606341Abstract: A CAN device is provided with an encryption function and a decryption function. The encryption function allows messages to be encrypted and put onto a CAN bus. The decryption function allows the messages on the CAN bus to be decrypted. The encryption and decryption functions share keys which change over the course of time.Type: GrantFiled: December 7, 2020Date of Patent: March 14, 2023Assignees: STMicroelectronics (Grenoble 2) SAS, TECHNOLOGICAL EDUCATIONAL INSTITUTE OF CRETE, Energica Motor Company S.p.A.Inventors: Antonio-Marcello Coppola, Georgios Kornaros, Giovanni Gherardi
-
Patent number: 11354251Abstract: A method of offloading a computing kernel from a host central processing unit (CPU) to a co-processor includes obtaining, by an application running on the host CPU, a virtual address of a packet in a user level queue of a general packet processing unit (GPPU) and initializing, by the application, the packet referenced by the virtual address using an application programming interface of a user level device driver (ULDD). The packet includes a plurality of handles corresponding to the computing kernel. The method further includes finalizing, by the ULDD, the packet by including a list of bootstrap translation addresses comprising a physical address and a virtual address for each of the plurality of handles and output by a kernel level device driver (KLDD) of an operating system running on the host CPU, and accessing, by the application using the virtual address, results obtained from the co-processor processing the computing kernel.Type: GrantFiled: April 1, 2021Date of Patent: June 7, 2022Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, TECHNOLOGICAL EDUCATIONAL INSTITUTE OF CRETEInventors: Antonio-Marcello Coppola, Georgios Kornaros, Miltos Grammatikakis
-
Publication number: 20210224196Abstract: A method of offloading a computing kernel from a host central processing unit (CPU) to a co-processor includes obtaining, by an application running on the host CPU, a virtual address of a packet in a user level queue of a general packet processing unit (GPPU) and initializing, by the application, the packet referenced by the virtual address using an application programming interface of a user level device driver (ULDD). The packet includes a plurality of handles corresponding to the computing kernel. The method further includes finalizing, by the ULDD, the packet by including a list of bootstrap translation addresses comprising a physical address and a virtual address for each of the plurality of handles and output by a kernel level device driver (KLDD) of an operating system running on the host CPU, and accessing, by the application using the virtual address, results obtained from the co-processor processing the computing kernel.Type: ApplicationFiled: April 1, 2021Publication date: July 22, 2021Inventors: Antonio-Marcello Coppola, Georgios Kornaros, Miltos Grammatikakis
-
Publication number: 20210119981Abstract: A CAN device is provided with an encryption function and a decryption function. The encryption function allows messages to be encrypted and put onto a CAN bus. The decryption function allows the messages on the CAN bus to be decrypted. The encryption and decryption functions share keys which change over the course of time.Type: ApplicationFiled: December 7, 2020Publication date: April 22, 2021Inventors: Antonio-Marcello Coppola, Georgios Kornaros, Giovanni Gherardi
-
Patent number: 10970229Abstract: An apparatus includes a first processor to execute a user-level application to operate in a virtual address, and a co-processor to execute a computing kernel associated with user-level application elements to be performed on the co-processor. The computing kernel is to operate in the virtual address. A memory includes physical addresses, and a partition used to map the virtual address associated with the first processor and to map the virtual address associated with the co-processor. A packet processor manages communications between the first processor and the co-processor. The packet processor receives packets from the first processor, with the packets including memory addresses identifying code and data of the computing kernel. The packet processor stores the packets in a queue associated with the user-level application, and outputs the packets to the co-processor, such that the co-processor is enabled to execute the computing kernel.Type: GrantFiled: March 8, 2019Date of Patent: April 6, 2021Assignees: STMICROELECTRONICS (GRENOLBE 2) SAS, TECHNOLOGICAL EDUCATIONAL INSTITUTE OF CRETEInventors: Antonio-Marcello Coppola, Georgios Kornaros, Miltos Grammatikakis
-
Patent number: 10862874Abstract: A CAN device is provided with an encryption function and a decryption function. The encryption function allows messages to be encrypted and put onto a CAN bus. The decryption function allows the messages on the CAN bus to be decrypted. The encryption and decryption functions share keys which change over the course of time.Type: GrantFiled: March 29, 2018Date of Patent: December 8, 2020Assignees: STMicroelectronics (Grenoble 2) SAS, TECHNOLOGICAL EDUCATIONAL INSTITUTE OF CRETE, Energica Motor Company S.p.A.Inventors: Antonio-Marcello Coppola, Georgios Kornaros, Giovanni Gherardi
-
Patent number: 10826880Abstract: A CAN device is provided with an encryption function and a decryption function. The encryption function allows messages to be encrypted and put onto a CAN bus. The decryption function allows the messages on the CAN bus to be decrypted. The encryption and decryption functions share keys which change over the course of time.Type: GrantFiled: March 29, 2018Date of Patent: November 3, 2020Assignees: STMicroelectronics (Grenoble 2) SAS, TECHNOLOGICAL EDUCATIONAL INSTITUTE OF CRETE, Energica Motor Company S.p.A.Inventors: Antonio-Marcello Coppola, Georgios Kornaros, Giovanni Gherardi
-
Publication number: 20190205260Abstract: An apparatus includes a first processor to execute a user-level application to operate in a virtual address, and a co-processor to execute a computing kernel associated with user-level application elements to be performed on the co-processor. The computing kernel is to operate in the virtual address. A memory includes physical addresses, and a partition used to map the virtual address associated with the first processor and to map the virtual address associated with the co-processor. A packet processor manages communications between the first processor and the co-processor. The packet processor receives packets from the first processor, with the packets including memory addresses identifying code and data of the computing kernel. The packet processor stores the packets in a queue associated with the user-level application, and outputs the packets to the co-processor, such that the co-processor is enabled to execute the computing kernel.Type: ApplicationFiled: March 8, 2019Publication date: July 4, 2019Inventors: Antonio-Marcello Coppola, Georgios Kornaros, Miltos Grammatikakis
-
Patent number: 10261912Abstract: An apparatus includes a first processor to execute a user-level application to operate in a virtual address, and a co-processor to execute a computing kernel associated with user-level application elements to be performed on the co-processor. The computing kernel is to operate in the virtual address. A memory includes physical addresses, and a partition used to map the virtual address associated with the first processor and to map the virtual address associated with the co-processor. A packet processor manages communications between the first processor and the co-processor. The packet processor receives packets from the first processor, with the packets including memory addresses identifying code and data of the computing kernel. The packet processor stores the packets in a queue associated with the user-level application, and outputs the packets to the co-processor, such that the co-processor is enabled to execute the computing kernel.Type: GrantFiled: January 10, 2017Date of Patent: April 16, 2019Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, TECHNOLOGICAL EDUCATIONAL INSTITUTE OF CRETEInventors: Antonio-Marcello Coppola, Georgios Kornaros, Miltos Grammatikakis
-
Publication number: 20180295112Abstract: A CAN device is provided with an encryption function and a decryption function. The encryption function allows messages to be encrypted and put onto a CAN bus. The decryption function allows the messages on the CAN bus to be decrypted. The encryption and decryption functions share keys which change over the course of time.Type: ApplicationFiled: March 29, 2018Publication date: October 11, 2018Inventors: Antonio-Marcello Coppola, Georgios Kornaros, Giovanni Gherardi
-
Publication number: 20170206169Abstract: An apparatus includes a first processor to execute a user-level application to operate in a virtual address, and a co-processor to execute a computing kernel associated with user-level application elements to be performed on the co-processor. The computing kernel is to operate in the virtual address. A memory includes physical addresses, and a partition used to map the virtual address associated with the first processor and to map the virtual address associated with the co-processor. A packet processor manages communications between the first processor and the co-processor. The packet processor receives packets from the first processor, with the packets including memory addresses identifying code and data of the computing kernel. The packet processor stores the packets in a queue associated with the user-level application, and outputs the packets to the co-processor, such that the co-processor is enabled to execute the computing kernel.Type: ApplicationFiled: January 10, 2017Publication date: July 20, 2017Inventors: Antonio-Marcello COPPOLA, Georgios Kornaros, Miltos Grammatikakis
-
Patent number: 9519596Abstract: A method for controlling access of a processor to a resource, wherein the processor has an instruction set including a virtualization extension, may include executing a resource access instruction by the processor using the virtualization extension, whereby the resource access instruction conveys a virtual address (VA) and a virtual machine identifier. The method may also include translating the virtual address to a physical address based on the virtual machine identifier, and looking-up an access control rule table using the physical address as a search key. Each entry of the rule table includes a virtual machine identifier. The method further includes controlling access to the resource based on the output of the rule table and a match between the virtual machine identifier returned by the table and the virtual machine identifier conveyed in the resource access instruction.Type: GrantFiled: February 24, 2015Date of Patent: December 13, 2016Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, TECHNOLOGICAL EDUCATIONAL INSTITUTE OF CRETEInventors: Antonio-Marcello Coppola, Georgios Kornaros, Miltos Grammatikakis
-
Patent number: 9461913Abstract: Embodiments relate to a method for transmitting a message in a data path of a network, the method includes transmitting a message onto an input bus of an input interface module, the message being received in flits of a size corresponding to the width of the input bus and generating a validity indicator for each elementary flit constituting each flit received. The message is transmitted onto an output bus of the input interface module towards a receiving interface module in flits of a size corresponding to the width of the output bus along with each validity indicator generated in association with the corresponding elementary flit. The receiving interface module receives flits constituting the message and the associated validity indicators and rejects a received flit if an elementary flit of the received flit is associated with a validity indicator in the invalid state.Type: GrantFiled: May 14, 2013Date of Patent: October 4, 2016Assignee: STMicroelectronics (Grenoble 2) SASInventors: Michael Soulie, Riccardo Locatelli, Antonio-Marcello Coppola
-
Publication number: 20150254189Abstract: A method for controlling access of a processor to a resource, wherein the processor has an instruction set including a virtualization extension, may include executing a resource access instruction by the processor using the virtualization extension, whereby the resource access instruction conveys a virtual address (VA) and a virtual machine identifier. The method may also include translating the virtual address to a physical address based on the virtual machine identifier, and looking-up an access control rule table using the physical address as a search key. Each entry of the rule table includes a virtual machine identifier. The method further includes controlling access to the resource based on the output of the rule table and a match between the virtual machine identifier returned by the table and the virtual machine identifier conveyed in the resource access instruction.Type: ApplicationFiled: February 24, 2015Publication date: September 10, 2015Inventors: Antonio-Marcello Coppola, Georgios Kornaros, Miltos Grammatikakis
-
Patent number: 8825986Abstract: A switch includes at least one input configured to receive data and at least two outputs configured to send data to at least two further switches in a network via at least two output links. Each output link has a known hop value. The switch further includes a direction determinator that determines a routing direction for the data from information identifying a relative location of the switch in the network and information identifying a destination of said data. A distributor within the switch processes the routing direction and direction information about each output link in order to select one of said at least two outputs for outputting said data. The selection that is made prioritizes output links for selection which have relatively higher known hop values.Type: GrantFiled: October 13, 2011Date of Patent: September 2, 2014Assignee: STMicroelectronics (Grenoble 2) SASInventors: Antonio-Marcello Coppola, Riccardo Locatelli, Jose Flich Cardo, Jose Cano Reyes, Jose Francisco Duato Marin
-
Publication number: 20130301643Abstract: Embodiments relate to a method for transmitting a message in a data path of a network, the method includes transmitting a message onto an input bus of an input interface module, the message being received in flits of a size corresponding to the width of the input bus and generating a validity indicator for each elementary flit constituting each flit received. The message is transmitted onto an output bus of the input interface module towards a receiving interface module in flits of a size corresponding to the width of the output bus along with each validity indicator generated in association with the corresponding elementary flit. The receiving interface module receives flits constituting the message and the associated validity indicators and rejects a received flit if an elementary flit of the received flit is associated with a validity indicator in the invalid state.Type: ApplicationFiled: May 14, 2013Publication date: November 14, 2013Inventors: Michael Soulie, Riccardo Locatelli, Antonio-Marcello Coppola
-
Patent number: 8352628Abstract: A method is for transferring data from a source target to a destination target in a network. The method includes sending at least one request packet for the destination target, with the request packet containing information relating to a first address where data are located and a second address where data are to be stored. Moreover, at least one transaction request is sent to the source target, with the read request being elaborated from information contained in the request packet. The source target transfers the data located at the first address to the second address.Type: GrantFiled: June 20, 2008Date of Patent: January 8, 2013Assignee: STMicroelectronics SAInventors: Giuseppe Maruccia, Riccardo Locatelli, Lorenzo Pieralisi, Marcello Coppola
-
Publication number: 20120134364Abstract: A switch includes at least one input configured to receive data and at least two outputs configured to send data to at least two further switches in a network via at least two output links. Each output link has a known hop value. The switch further includes a direction determinator that determines a routing direction for the data from information identifying a relative location of the switch in the network and information identifying a destination of said data. A distributor within the switch processes the routing direction and direction information about each output link in order to select one of said at least two outputs for outputting said data. The selection that is made prioritizes output links for selection which have relatively higher known hop values.Type: ApplicationFiled: October 13, 2011Publication date: May 31, 2012Inventors: Antonio-Marcello Coppola, Riccardo Locatelli, Jose Flich Cardo, Jose Cano Reyes, Jose Francisco Duato Marin
-
Patent number: 8185934Abstract: A data protection device for an interconnect network on chip (NoC) includes a header encoder that receives input requests for generating network packets. The encoder routes the input requests to a destination address. An access control unit controls and allows access to the destination address. The access control unit uses a memory to store access rules for controlling access to the network as a function of the destination address and of a source of the input request.Type: GrantFiled: September 9, 2008Date of Patent: May 22, 2012Assignee: STMicroelectronics (Grenoble) SASInventors: Valerio Catalano, Marcello Coppola, Riccardo Locatelli, Cristina Silvano, Gianluca Palermo, Leandro Fiorin
-
Patent number: 8165120Abstract: This method for transferring data through a network on chip (NoC) between a first electronic device and a second electronic device, comprising: retrieving from the first device request packets comprising request control data for controlling data transfer and actual request data to be transferred; storing said request control and data to be transferred in memory means provided in an network interface (NI); and elaborating data packets to be transferred to the second device through said network, said data packets comprising a header and a payload elaborated from said control data and said actual data, respectively; The control data and the actual data to be transferred are stored in separate first and second memory means.Type: GrantFiled: November 10, 2008Date of Patent: April 24, 2012Assignee: STMicroelectronics (Grenoble) SASInventors: Giuseppe Maruccia, Riccardo Locatelli, Lorenzo Pieralisi, Marcello Coppola