Patents by Inventor Marcello Melgara

Marcello Melgara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4823307
    Abstract: The control unit detects the errors concurrently with normal microinstruction execution through suitable internal checking circuits and a determined microinstruction allocation in the memory. Microinstructions comprise additional fields (CS, FS) carrying the encoding, in Modified Berger code, of the allocation address of the microinstruction itself and of the following one. The microinstructions of destination of conditional jumps are allocated so that their codes are related to each other by simple logic relationships which are then reproduced by an internal circuit (CSM). The two fields, the one of the next microinstruction being duly delayed, are then compared and possible differences represent unidirectional and incorrect sequencing errors. The other errors are detected through particular implementations of some internal circuits (STK1, INC1) and duplication of others (RCT, SEL).
    Type: Grant
    Filed: March 12, 1986
    Date of Patent: April 18, 1989
    Assignee: Cselt - Centro Studi e Laboratori Telecomunicazioni S.P.A.
    Inventors: Marcello Melgara, Maurizio Paolini, Maura Torolla
  • Patent number: 4709340
    Abstract: Speech synthesis is selectable in two modes: "normal" mode in which the synthesis filter is responsive to prestored parameters, and "test" mode which executes a checking procedure based on test words from an outside source. Each mode has corresponding instructions prestored in a memory.
    Type: Grant
    Filed: June 11, 1984
    Date of Patent: November 24, 1987
    Assignee: CSELT-Centro Studi e Laboratori Telecomunicazioni S.p.A.
    Inventors: Giuseppe N. Capizzi, Cesario Cianci, Marcello Melgara
  • Patent number: 4621342
    Abstract: A circuit arrangement for deciding concurrent requests for access to a common data bus emitted by a number n=2.sup.m of components of different ranks, specifically multiprocessor elements, comprises n mutually identical arbitration devices respectively associated with these components. The arbitration devices are interconnected in a chain by a priority bus of branched binary structure divided into m lines connected, within each device, to a logic network that is also connected to an internal m-conductor bus extending from a priority-code register. The priority bus, whose lines are normally at zero potential, is connected in any given device to the register thereof in the presence of an access request from the associated component whereupon its logic network determines whether the code on that bus equals the contents of the register; if so, the associated component is enabled by a control unit of the device to access the data bus.
    Type: Grant
    Filed: February 1, 1984
    Date of Patent: November 4, 1986
    Assignee: CSELT Centro Studi E Laboratori Telecomunicazioni S.p.A.
    Inventors: Giuseppe N. Capizzi, Marcello Melgara