Patents by Inventor Marcelo A. Kuroda
Marcelo A. Kuroda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250027902Abstract: In at least one illustrative embodiment, a field-effect transistor biosensor for detection of a pathogen includes a substrate and a channel formed from a two-dimensional monolayer or few-layer metal chalcogenide that is functionalized with a biorecognition element. The biorecognition element may be an antibody, such as an antibody for the SARS-COV-2 spike protein. A method for manufacturing the biosensor includes depositing an amorphous two-dimensional material on the substrate with pulsed laser ablation, crystallizing the amorphous two-dimensional material to generate a two-dimensional monolayer coupled to the substrate, and activating a surface of the two-dimensional material with the biorecognition element after crystallizing the amorphous two-dimensional material. The composition of the two-dimensional material may be tuned. The substrate may be photolithographically patterned. Other embodiments are described and claimed.Type: ApplicationFiled: October 8, 2024Publication date: January 23, 2025Inventors: Masoud MAHJOURI-SAMANI, Michael C. HAMILTON, Marcelo A. KURODA, Sahar HASIM, Parvin FATHI-HAFSHEJANI
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Patent number: 12123845Abstract: In at least one illustrative embodiment, a field-effect transistor biosensor for detection of a pathogen includes a substrate and a channel formed from a two-dimensional monolayer or few-layer metal chalcogenide that is functionalized with a biorecognition element. The biorecognition element may be an antibody, such as an antibody for the SARS-CoV-2 spike protein. A method for manufacturing the biosensor includes depositing an amorphous two-dimensional material on the substrate with pulsed laser ablation, crystallizing the amorphous two-dimensional material to generate a two-dimensional monolayer coupled to the substrate, and activating a surface of the two-dimensional material with the biorecognition element after crystallizing the amorphous two-dimensional material. The composition of the two-dimensional material may be tuned. The substrate may be photolithographically patterned. Other embodiments are described and claimed.Type: GrantFiled: November 9, 2021Date of Patent: October 22, 2024Assignees: AUBURN UNIVERSITY, MERCER UNIVERSITYInventors: Masoud Mahjouri-Samani, Michael C. Hamilton, Marcelo Kuroda, Sahar Hasim, Parvin Fathi-Hafshejani
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Publication number: 20220146451Abstract: In at least one illustrative embodiment, a field-effect transistor biosensor for detection of a pathogen includes a substrate and a channel formed from a two-dimensional monolayer or few-layer metal chalcogenide that is functionalized with a biorecognition element. The biorecognition element may be an antibody, such as an antibody for the SARS-CoV-2 spike protein. A method for manufacturing the biosensor includes depositing an amorphous two-dimensional material on the substrate with pulsed laser ablation, crystallizing the amorphous two-dimensional material to generate a two-dimensional monolayer coupled to the substrate, and activating a surface of the two-dimensional material with the biorecognition element after crystallizing the amorphous two-dimensional material. The composition of the two-dimensional material may be tuned. The substrate may be photolithographically patterned. Other embodiments are described and claimed.Type: ApplicationFiled: November 9, 2021Publication date: May 12, 2022Inventors: MASOUD MAHJOURI-SAMANI, MICHAEL C. HAMILTON, MARCELO KURODA, SAHAR HASIM, PARVIN FATHI-HAFSHEJANI
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Patent number: 10964881Abstract: A piezoelectronic device with novel force amplification includes a first electrode; a piezoelectric layer disposed on the first electrode; a second electrode disposed on the piezoelectric layer; an insulator disposed on the second electrode; a piezoresistive layer disposed on the insulator; a third electrode disposed on the insulator; a fourth electrode disposed on the insulator; a semi-rigid housing surrounding the layers and the electrodes; wherein the semi-rigid housing is in contact with the first, third, and fourth electrodes and the piezoresistive layer; wherein the semi-rigid housing includes a void. The third and fourth electrodes are on the same plane and separated from each other in the transverse direction by a distance.Type: GrantFiled: November 29, 2017Date of Patent: March 30, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce G. Elmegreen, Marcelo A. Kuroda, Xiao Hu Liu, Glenn J. Martyna, Dennis M. Newns, Paul M. Solomon
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Patent number: 9941472Abstract: A piezoelectronic device with novel force amplification includes a first electrode; a piezoelectric layer disposed on the first electrode; a second electrode disposed on the piezoelectric layer; an insulator disposed on the second electrode; a piezoresistive layer disposed on the insulator; a third electrode disposed on the insulator; a fourth electrode disposed on the insulator; a semi-rigid housing surrounding the layers and the electrodes; wherein the semi-rigid housing is in contact with the first, third, and fourth electrodes and the piezoresistive layer; wherein the semi-rigid housing includes a void. The third and fourth electrodes are on the same plane and separated from each other in the transverse direction by a distance.Type: GrantFiled: December 19, 2014Date of Patent: April 10, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce G. Elmegreen, Marcelo A. Kuroda, Xiao Hu Liu, Glenn J. Martyna, Dennis M. Newns, Paul M. Solomon
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Publication number: 20180090681Abstract: A piezoelectronic device with novel force amplification includes a first electrode; a piezoelectric layer disposed on the first electrode; a second electrode disposed on the piezoelectric layer; an insulator disposed on the second electrode; a piezoresistive layer disposed on the insulator; a third electrode disposed on the insulator; a fourth electrode disposed on the insulator; a semi-rigid housing surrounding the layers and the electrodes; wherein the semi-rigid housing is in contact with the first, third, and fourth electrodes and the piezoresistive layer; wherein the semi-rigid housing includes a void. The third and fourth electrodes are on the same plane and separated from each other in the transverse direction by a distance.Type: ApplicationFiled: November 29, 2017Publication date: March 29, 2018Inventors: Bruce G. Elmegreen, Marcelo A. Kuroda, Xiao Hu Liu, Glenn J. Martyna, Dennis M. Newns, Paul M. Solomon
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Patent number: 9444029Abstract: A method of forming a piezoelectronic transistor (PET), the PET, and a semiconductor device including the PET are described. The method includes forming a piezoelectric (PE) element with a trench and forming a pair of electrodes on the PE element in a coplanar arrangement in a first plane, both of the pair of electrodes being on a same side of the PE element. The method also includes forming a piezoresistive (PR) element above the pair of electrodes and forming a clamp above the PR element. Applying a voltage to the pair of electrodes causes displacement of the PE element perpendicular to the first plane.Type: GrantFiled: June 23, 2015Date of Patent: September 13, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian A. Bryce, Josephine B. Chang, Marcelo A. Kuroda
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Patent number: 9419203Abstract: A method of forming a piezoelectronic transistor (PET) device, the PET device, and a semiconductor including the PET device are described. The method includes forming a first metal layer, forming a layer of a piezoelectric (PE) element on the first metal layer, and forming a second metal layer on the PE element. The method also includes forming a well above the second metal layer, forming a piezoresistive (PR) material in the well and above the well, and forming a passivation layer and a top metal layer above the PR material at the diameter of the PR material above the well, wherein a cross sectional shape of the well, the PR material above the well, the passivation layer, and the top metal layer is a T-shaped structure. The method further includes forming a metal clamp layer as a top layer of the PET device.Type: GrantFiled: June 23, 2015Date of Patent: August 16, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian A. Bryce, Josephine B. Chang, Matthew W. Copel, Marcelo A. Kuroda
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Patent number: 9419201Abstract: A semiconductor device, a piezoelectronic transistor (PET) device, and a method of fabricating the PET device are described. The method includes forming a first stack of dielectric layers, forming a first metal layer over the first stack, forming a piezoelectric (PE) material on the first metal layer, and forming a second metal layer on the PE material. The method also includes forming a piezoresistive (PR) element on the second metal layer through a gap in a first membrane formed a distance d above the second metal layer.Type: GrantFiled: June 23, 2015Date of Patent: August 16, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian A. Bryce, Josephine B. Chang, Matthew W. Copel, Marcelo A. Kuroda
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Publication number: 20160126446Abstract: A method of forming a piezoelectronic transistor (PET) device, the PET device, and a semiconductor including the PET device are described. The method includes forming a first metal layer, forming a layer of a piezoelectric (PE) element on the first metal layer, and forming a second metal layer on the PE element. The method also includes forming a well above the second metal layer, forming a piezoresistive (PR) material in the well and above the well, and forming a passivation layer and a top metal layer above the PR material at the diameter of the PR material above the well, wherein a cross sectional shape of the well, the PR material above the well, the passivation layer, and the top metal layer is a T-shaped structure. The method further includes forming a metal clamp layer as a top layer of the PET device.Type: ApplicationFiled: June 23, 2015Publication date: May 5, 2016Inventors: Brian A. Bryce, Josephine B. Chang, Matthew W. Copel, Marcelo A. Kuroda
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Publication number: 20160126447Abstract: A method of forming a piezoelectronic transistor (PET), the PET, and a semiconductor device including the PET are described. The method includes forming a piezoelectric (PE) element with a trench and forming a pair of electrodes on the PE element in a coplanar arrangement in a first plane, both of the pair of electrodes being on a same side of the PE element. The method also includes forming a piezoresistive (PR) element above the pair of electrodes and forming a clamp above the PR element. Applying a voltage to the pair of electrodes causes displacement of the PE element perpendicular to the first plane.Type: ApplicationFiled: June 23, 2015Publication date: May 5, 2016Inventors: Brian A. Bryce, Josephine B. Chang, Marcelo A. Kuroda
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Publication number: 20160126448Abstract: A semiconductor device, a piezoelectronic transistor (PET) device, and a method of fabricating the PET device are described. The method includes forming a first stack of dielectric layers, forming a first metal layer over the first stack, forming a piezoelectric (PE) material on the first metal layer, and forming a second metal layer on the PE material. The method also includes forming a piezoresistive (PR) element on the second metal layer through a gap in a first membrane formed a distance d above the second metal layer.Type: ApplicationFiled: June 23, 2015Publication date: May 5, 2016Inventors: Brian A. Bryce, Josephine B. Chang, Matthew W. Copel, Marcelo A. Kuroda
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Patent number: 9293687Abstract: A method of forming a piezoelectronic transistor (PET) device, the PET device, and a semiconductor including the PET device are described. The method includes forming a first metal layer, forming a layer of a piezoelectric (PE) element on the first metal layer, and forming a second metal layer on the PE element. The method also includes forming a well above the second metal layer, forming a piezoresistive (PR) material in the well and above the well, and forming a passivation layer and a top metal layer above the PR material at the diameter of the PR material above the well, wherein a cross sectional shape of the well, the PR material above the well, the passivation layer, and the top metal layer is a T-shaped structure. The method further includes forming a metal clamp layer as a top layer of the PET device.Type: GrantFiled: October 31, 2014Date of Patent: March 22, 2016Assignee: International Business Machines CorporationInventors: Brian A. Bryce, Josephine B. Chang, Matthew W. Copel, Marcelo A. Kuroda
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Patent number: 9287489Abstract: A method of forming a piezoelectronic transistor (PET), the PET, and a semiconductor device including the PET are described. The method includes forming a piezoelectric (PE) element with a trench and forming a pair of electrodes on the PE element in a coplanar arrangement in a first plane, both of the pair of electrodes being on a same side of the PE element. The method also includes forming a piezoresistive (PR) element above the pair of electrodes and forming a clamp above the PR element. Applying a voltage to the pair of electrodes causes displacement of the PE element perpendicular to the first plane.Type: GrantFiled: October 31, 2014Date of Patent: March 15, 2016Assignee: International Business Machines CorporationInventors: Brian A. Bryce, Josephine B. Chang, Marcelo A. Kuroda
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Patent number: 9263664Abstract: A semiconductor device, a piezoelectronic transistor (PET) device, and a method of fabricating the PET device are described. The method includes forming a first stack of dielectric layers, forming a first metal layer over the first stack, forming a piezoelectric (PE) material on the first metal layer, and forming a second metal layer on the PE material. The method also includes forming a piezoresistive (PR) element on the second metal layer through a gap in a first membrane formed a distance d above the second metal layer.Type: GrantFiled: October 31, 2014Date of Patent: February 16, 2016Assignee: International Business Machines CorporationInventors: Brian A. Bryce, Josephine B. Chang, Matthew W. Copel, Marcelo A. Kuroda
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Publication number: 20150255699Abstract: A piezoelectronic device with novel force amplification includes a first electrode; a piezoelectric layer disposed on the first electrode; a second electrode disposed on the piezoelectric layer; an insulator disposed on the second electrode; a piezoresistive layer disposed on the insulator; a third electrode disposed on the insulator; a fourth electrode disposed on the insulator; a semi-rigid housing surrounding the layers and the electrodes; wherein the semi-rigid housing is in contact with the first, third, and fourth electrodes and the piezoresistive layer; wherein the semi-rigid housing includes a void. The third and fourth electrodes are on the same plane and separated from each other in the transverse direction by a distance.Type: ApplicationFiled: December 19, 2014Publication date: September 10, 2015Inventors: Bruce G. Elmegreen, Marcelo A. Kuroda, Xiao Hu Liu, Glenn J. Martyna, Dennis M. Newns, Paul M. Solomon
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Publication number: 20120000521Abstract: A solar cell includes a semiconductor portion, a graphene layer disposed on a first surface of the semiconductor portion, and a first conductive layer patterned on the graphene layer, the first conductive layer including at least one bus bar portion, a plurality of fingers extending from the at least one bus bar portion, and a refractive layer disposed on the first conductive layer.Type: ApplicationFiled: July 1, 2010Publication date: January 5, 2012Applicants: EGYPT NANOTECHNOLOGY CENTER, INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ageeth A. Bol, Amal Kasry, Marcelo Kuroda, Ahmed Maarouf, Glenn J. Martyna, Dennis M. Newns, Razvan A. Nistor, George S. Tulevski