Patents by Inventor Marcelo De Maria

Marcelo De Maria has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7277429
    Abstract: A switch fabric implemented on a chip includes an array of cells and an I/O interface in communication with the array of cells for permitting exchange of data packets between said array of cells and components external to said array of cells. Each cell communicates with at least one other cell of the array, thereby permitting an exchange of data packets to take place between the cells of the array. Each cell includes a memory for receiving a data packet from another cell of the array as well as a control entity to control release of a data packet toward a selected destination cell of the array at least in part on a basis of a degree of occupancy of the memory in the destination cell. In this way, scheduling is distributed amongst the cells of the switch fabric.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: October 2, 2007
    Assignee: 4198638 Canada Inc.
    Inventors: Richard S. Norman, Marcelo De Maria, Sébastien Côté, Carl Langlois, John Haughey, Yves Boudreault
  • Patent number: 7197042
    Abstract: A router includes a routing layer and a switching layer. The routing layer includes a plurality of I/O ports for exchanging data with components external to the router. The switching layer is adapted to switch data packets between I/O ports of the routing layer. The switching layer includes an array of cells in communication with the routing layer for permitting exchange of data packets between the array of cells and the routing layer. Each cell includes a memory for receiving a data packet from the routing layer. The routing layer includes a controller to control release of a data packet toward a cell of the array at least in part on a basis of a degree of occupancy of the memory in the cell.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: March 27, 2007
    Assignee: 4198638 Canada Inc.
    Inventors: Richard S. Norman, Marcelo De Maria, Sébastien Côté, Carl Langlois
  • Publication number: 20060239259
    Abstract: A switch fabric implemented on a chip includes an array of cells and an I/O interface in communication with the array of cells permitting exchange of data packets between the array of cells and components external to the array of cells. Each cell communicates with at least one other cell of the array, thereby permitting exchange of data packets between the cells of the array. Each cell includes a memory for holding a plurality of data packets for transmission to other cells of said array. Each data packet of the plurality of data packets has a characteristic element represented by a parameter, the parameter allowing one data packet to be distinguished from another data packet in the plurality of data packets. Each cell further includes a control entity operative to select at least one data packet from the plurality of data packets at least in part on a basis of the parameter and to transmit the selected data packet to another cell of said array of cells.
    Type: Application
    Filed: June 26, 2006
    Publication date: October 26, 2006
    Inventors: Richard Norman, Marcelo De Maria, Sebastien Cote, Carl Langlois, John Haughey, Yves Boudreault
  • Patent number: 6990096
    Abstract: A switch fabric implemented on a chip includes an array of cells and an I/O interface in communication with the array of cells for permitting exchange of data packets between the array of cells and components external to the array of cells. Each cell includes a transmitter in communication with the I/O interface and in communication with every other cell of the array, the transmitter being operative to process a data packet received from the I/O interface to determine a destination of the data packet and forward the data packet to at least one cell of the array selected on a basis of the determined destination. Each cell further includes a plurality of receivers associated with respective cells from the array, each receiver being in communication with a respective cell allowing the respective cell to forward data packets to the receiver, where the receivers are in communication with the I/O interface for releasing data packets to the I/O interface.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: January 24, 2006
    Assignee: 4198638 Canada Inc.
    Inventors: Richard S. Norman, Marcelo De Maria, Sébastien Côté, Carl Langlois, John Haughey, Yves Boudreault
  • Patent number: 6990097
    Abstract: A switch fabric implemented on a chip includes an array of cells and an I/O interface in communication with the array of cells for permitting exchange of data packets between the array of cells and components external to the array of cells. Each cell communicates with at least one other cell of the array, permitting an exchange of data packets between the cells of the array and an exchange of control information between the cells of the array. Each cell is operative to control transmission of data packets to other cells of the array at least in part on a basis of the control information. The control information is thus used to regulate the flow of data packets between cells.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: January 24, 2006
    Assignee: 4198638 Canada Inc.
    Inventors: Richard S. Norman, Marcelo De Maria, Sébastien Côté, Carl Langlois, John Haughey, Yves Boudreault
  • Publication number: 20030043742
    Abstract: A method and system for regulating packet flow to a downstream entity capable of forwarding packets to a plurality of intermediate destinations. The method includes maintaining a database of queues, each queue in the database being associated with packets intended to be forwarded to a corresponding one of a plurality of final destinations via a corresponding one of the intermediate destinations. Each queue in the database is further associated with a state that is either active or inactive. Upon receipt of a message from the downstream entity indicating a reduced (increased) ability of a particular one of the intermediate destinations to accept packets intended to be forwarded to a particular one of the final destinations, the method provides for rendering inactive (active) the state of the queue associated with packets intended to be forwarded to the particular final destination via the particular intermediate destination.
    Type: Application
    Filed: August 31, 2001
    Publication date: March 6, 2003
    Inventors: Marcelo De Maria, Richard S. Norman, Jean Belanger, Eyad Saheb
  • Publication number: 20020181440
    Abstract: A router includes a routing layer and a switching layer. The routing layer includes a plurality of I/O ports for exchanging data with components external to the router. The switching layer is adapted to switch data packets between I/O ports of the routing layer. The switching layer includes an array of cells in communication with the routing layer for permitting exchange of data packets between the array of cells and the routing layer. Each cell includes a memory for receiving a data packet from the routing layer. The routing layer includes a controller to control release of a data packet toward a cell of the array at least in part on a basis of a degree of occupancy of the memory in the cell.
    Type: Application
    Filed: June 1, 2001
    Publication date: December 5, 2002
    Inventors: Richard S. Norman, Marcelo De Maria, Sebastien Cote, Carl Langlois
  • Publication number: 20020181453
    Abstract: A switch fabric implemented on a chip includes an array of cells and an I/O interface in communication with the array of cells permitting exchange of data packets between the array of cells and components external to the array of cells. Each cell communicates with at least one other cell of the array, thereby permitting exchange of data packets between the cells of the array. Each cell includes a memory for holding a plurality of data packets for transmission to other cells of said array. Each data packet of the plurality of data packets has a characteristic element represented by a parameter, the parameter allowing one data packet to be distinguished from another data packet in the plurality of data packets. Each cell further includes a control entity operative to select at least one data packet from the plurality of data packets at least in part on a basis of the parameter and to transmit the selected data packet to another cell of said array of cells.
    Type: Application
    Filed: June 1, 2001
    Publication date: December 5, 2002
    Inventors: Richard S. Norman, Marcelo De Maria, Sebastien Cote, Carl Langlois, John Haughey, Yves Boudeault
  • Publication number: 20020181455
    Abstract: A switch fabric implemented on a chip includes an array of cells and an I/O interface in communication with the array of cells for permitting exchange of data packets between the array of cells and components external to the array of cells. Each cell communicates with at least one other cell of the array, permitting an exchange of data packets between the cells of the array and an exchange of control information between the cells of the array. Each cell is operative to control transmission of data packets to other cells of the array at least in part on a basis of the control information. The control information is thus used to regulate the flow of data packets between cells.
    Type: Application
    Filed: June 1, 2001
    Publication date: December 5, 2002
    Inventors: Richard S. Norman, Marcelo De Maria, Sebastien Cote, Carl Langlois, John Haughey, Yves Boudreault
  • Publication number: 20020181454
    Abstract: A switch fabric implemented on a chip includes an array of cells and an I/O interface in communication with the array of cells for permitting exchange of data packets between said array of cells and components external to said array of cells. Each cell communicates with at least one other cell of the array, thereby permitting an exchange of data packets to take place between the cells of the array. Each cell includes a memory for receiving a data packet from another cell of the array as well as a control entity to control release of a data packet toward a selected destination cell of the array at least in part on a basis of a degree of occupancy of the memory in the destination cell. In this way, scheduling is distributed amongst the cells of the switch fabric.
    Type: Application
    Filed: June 1, 2001
    Publication date: December 5, 2002
    Inventors: Richard S. Norman, Marcelo De Maria, Sebastien Cote, Carl Langlois, John Haughey, Yves Boudreault
  • Publication number: 20020181452
    Abstract: A switch fabric implemented on a chip includes an array of cells and an I/O interface in communication with the array of cells for permitting exchange of data packets between the array of cells and components external to the array of cells. Each cell includes a transmitter in communication with the I/O interface and in communication with every other cell of the array, the transmitter being operative to process a data packet received from the I/O interface to determine a destination of the data packet and forward the data packet to at least one cell of the array selected on a basis of the determined destination. Each cell further includes a plurality of receivers associated with respective cells from the array, each receiver being in communication with a respective cell allowing the respective cell to forward data packets to the receiver, where the receivers are in communication with the I/O interface for releasing data packets to the I/O interface.
    Type: Application
    Filed: June 1, 2001
    Publication date: December 5, 2002
    Inventors: Richard S. Norman, Marcelo De Maria, Sebastien Cote, Carl Langlois, John Haughey, Yves Boudreault