Abstract: An electronic entertainment device which allows an untrained vocalist or instrumentalist to easily synthesize an instrumental lead, and optionally, one or more harmonies, simultaneous with the lead, playing along with predefined background musical sequences. While the background parts to a song are being played by the device, or any outside musical player, the user plays the melody, or "lead", by humming, singing, whistling, or operating any tone-producing device, such as a musical instrument, into the device. The device then identifies the pitch, compares it with a table of allowable pitches, as dictated by predefined data associated with the background music, chooses an appropriate output tone, and drives a music synthesizer to play the chosen instrument at the determined pitch, in accordance with the allowable pitches. The note which is produced by the device is one which sounds pleasing in the context of the musical background.

Abstract: A digital logic buffer device for generating dual polarity analog signals is described. In the presently preferred embodiment, buffer receives the positive polarity analog output of a digital-to-analog converter (V.sub.DAC), and a sign bit. If the sign bit indicates that a positive polarity is required, the buffer will output approximately V.sub.DAC. If a negative polarity is required, aproximately -V.sub.DAC will be generated.

Abstract: An MOS integrated circuit digital-to-analog converter employing a plurality of generally parallel resistance strings. Decoding means and switching means provide an analog output from the resistance strings, this output passes through only two switches. The resistance strings may be closely fabricated on a substrate, thereby reducing the effects of processing variations. A unique layout for the converter array minimizes the effects of masking misalignments.

Abstract: An integrated circuit processor real time processing of analog signals is described. The programmable processor duplicates filters, waveform generators and non-linear functions, such as rectification, with a high degree of stability and at a relatively low cost. A two-port, random-access memory provides inputs to an arithmetic logic unit (ALU). One of these inputs is coupled through a scaler (shifter). This scaler in conjunction with the ALU provides efficient multiplication, particularly by coefficients. ALU overflows are handled in an unusual manner to eliminate additional processing time for overflows. In a typical application, the one chip processor, with its 192-word program, samples an input analog signal at the rate of 13,020 Hz and detects the 8 tones used in telephony.

Abstract: A redundant memory circuit for a memory array in which the memory has a preselected number of rows and columns having addresses associated therewith and decoders coupled thereto and one or more redundant rows or columns having initially unspecified addresses associated therewith and redundant decoders coupled thereto. The redundant memory circuit programs the redundant decoders coupled to the redundant rows or columns having initially unspecified addresses to match the addresses of defective rows or columns having addresses associated therewith and disables one or more of the defective rows or columns having addresses associated therewith.

Abstract: An MOS integrated circuit digital-to-analog converter employing a plurality of generally parallel resistance strings. Decoding means and switching means provide an analog output from the resistance strings, this output passes through only two switches. The resistance strings may be closely fabricated on a substrate, thereby reducing the effects of processing variations. A unique layout for the converter array minimizes the effects of masking misalignments.

Abstract: An MOS integrated circuit for providing a stable reference voltage. The voltage thresholds of an enhancement mode transistor and depletion mode transistor are substracted to provide the stable reference potential. The reference potential is stable for both temperature and power supply variations, including variations in a substrate biasing potential.

Abstract: A system and method for interconnecting a plurality of separate memories (on other circuits) on a wafer so as to electrically exclude defective memories and include operative memories. A single discretionary connection is associated with each of the separate memories and such connection is made (or broken) after a memory is tested. In addition to a bidirectional memory bus used for input/output data and addresses, the wafer includes a separate identity bus used to define the memory organization. The identity bus is interconnected by a plurality of incrementers, one associated with each memory. The signal on the identity bus is incremented by useable memories and such signal is compared to an address on the bidirectional memory bus to select memories in an organized manner.