Abstract: A method of identifying a cause of an anomalous feature measured from system circuitry on an integrated circuit (IC) chip, the IC chip comprising the system circuitry and monitoring circuitry for monitoring the system circuitry by measuring features of the system circuitry in each window of a series of windows, the method comprising: (i) from a set of windows prior to the anomalous window comprising the anomalous feature, identifying a candidate window set in which to search for the cause of the anomalous feature; (ii) for each of the measured features of the system circuitry: (a) calculating a first feature probability distribution of that measured feature for the candidate window set; (b) calculating a second feature probability distribution of that measured feature for window(s) not in the candidate window set; (c) comparing the first and second feature probability distributions; and (d) identifying that measured feature in the timeframe of the candidate window set as a cause of the anomalous feature if th

Abstract: A method of monitoring messages from a sensor using an integrated circuit is provided. The messages include data measured by that sensor. The method includes reading a first message from interconnect circuitry of the integrated circuit. The interconnect circuitry connects the sensor to one or more core devices configured to process the messages. A first hash value is calculated for the first message. The first hash value is compared to one or more prior hash values stored in a hash store. Each prior hash value of the one or more prior hash values corresponds to a message that was read from the interconnect circuitry prior to the first message. A corrective action is performed when a difference between the first hash value and at least one of the prior hash values stored in the hash store is below a predetermined threshold.

Abstract: A method of identifying a cause of an anomalous feature measured from system circuitry on an integrated circuit (IC) chip, the IC chip comprising the system circuitry and monitoring circuitry for monitoring the system circuitry by measuring features of the system circuitry in each window of a series of windows, the method comprising: (i) from a set of windows prior to the anomalous window comprising the anomalous feature, identifying a candidate window set in which to search for the cause of the anomalous feature; (ii) for each of the measured features of the system circuitry: (a) calculating a first feature probability distribution of that measured feature for the candidate window set; (b) calculating a second feature probability distribution of that measured feature for window(s) not in the candidate window set; (c) comparing the first and second feature probability distributions; and (d) identifying that measured feature in the timeframe of the candidate window set as a cause of the anomalous feature if th

Abstract: A method of detecting anomalous latencies in communications between components on an integrated circuit (IC) chip.

Abstract: One aspect of the disclosure provides a computer system. In one embodiment, the computer system comprises a clock generator, at least one processor, and a clock frequency controller. The clock generator is configured to provide a clock signal at a clock frequency. The at least one processor is configured to receive the clock signal and to operate at a speed dependent on the clock frequency. The clock frequency controller is configured to receive efficiency information indicating a current efficiency of the at least one processor. The clock frequency controller is further configured to receive a request from the processor for a target number of processor instructions to be handled in a particular time period. The clock frequency controller is further configured to output a frequency control signal to the clock generator for controlling the clock frequency in dependence thereon.

Abstract: One aspect of the disclosure provides a computer system. In one embodiment, the computer system comprises a clock generator, at least one processor, and a clock frequency controller. The clock generator is configured to provide a clock signal at a clock frequency. The at least one processor is configured to receive the clock signal and to operate at a speed dependent on the clock frequency. The clock frequency controller is configured to receive efficiency information indicating a current efficiency of the at least one processor. The clock frequency controller is further configured to receive a request from the processor for a target number of processor instructions to be handled in a particular time period. The clock frequency controller is further configured to output a frequency control signal to the clock generator for controlling the clock frequency in dependence thereon.