Patents by Inventor Marco Aurelio Cartas

Marco Aurelio Cartas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11948906
    Abstract: An integrated circuit (IC) die structure comprises a substrate material comprising silicon. Integrated circuitry is over a first side of the substrate material. A composite layer is in direct contact with a second side of the substrate material. The second side is opposite the first side. The composite layer comprises a first constituent material associated with a first linear coefficient of thermal expansion (CTE), and a first thermal conductivity exceeding that of the substrate. The composite layer also comprises a second constituent material associated with a second CTE that is lower than the first, and a second thermal conductivity exceeding that of the substrate.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Feras Eid, Joe Walczyk, Weihua Tang, Akhilesh Rallabandi, Marco Aurelio Cartas Ayala
  • Patent number: 11676873
    Abstract: Semiconductor packages having a sealant bridge between an integrated heat spreader and a package substrate are described. In an embodiment, a semiconductor package includes a sealant bridge anchoring the integrated heat spreader to the package substrate at locations within an overhang gap laterally between a semiconductor die and a sidewall of the integrated heat spreader. The sealant bridge extends between a top wall of the integrated heat spreader and a die side component, such as a functional electronic component or a non-functional component, or a satellite chip on the package substrate. The sealant bridge modulates warpage or stress in thermal interface material joints to reduce thermal degradation of the semiconductor package.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: June 13, 2023
    Assignee: Intel Corporation
    Inventors: Dinesh Padmanabhan Ramalekshmi Thanu, Hemanth K. Dhavaleswarapu, Venkata Suresh Guthikonda, John J. Beatty, Yonghao An, Marco Aurelio Cartas Ayala, Luke J. Garner, Peng Li
  • Patent number: 11670569
    Abstract: Disclosed herein are channeled lids for integrated circuit (IC) packages, as well as related methods and devices. For example, in some embodiments, an IC package may include a die between a lid and a package substrate. A bottom surface of the lid may include a channel that at least partially overlaps the die.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: June 6, 2023
    Assignee: Intel Corporation
    Inventors: Manish Dubey, Amitesh Saha, Marco Aurelio Cartas, Peng Li, Bamidele Daniel Falola
  • Publication number: 20210249375
    Abstract: An integrated circuit (IC) die structure comprises a substrate material comprising silicon. Integrated circuitry is over a first side of the substrate material. A composite layer is in direct contact with a second side of the substrate material. The second side is opposite the first side. The composite layer comprises a first constituent material associated with a first linear coefficient of thermal expansion (CTE), and a first thermal conductivity exceeding that of the substrate. The composite layer also comprises a second constituent material associated with a second CTE that is lower than the first, and a second thermal conductivity exceeding that of the substrate.
    Type: Application
    Filed: February 7, 2020
    Publication date: August 12, 2021
    Applicant: INTEL CORPORATION
    Inventors: Feras Eid, Joe Walczyk, Weihua Tang, Akhilesh Rallabandi, Marco Aurelio Cartas Ayala
  • Publication number: 20200395269
    Abstract: Disclosed herein are channeled lids for integrated circuit (IC) packages, as well as related methods and devices. For example, in some embodiments, an IC package may include a die between a lid and a package substrate. A bottom surface of the lid may include a channel that at least partially overlaps the die.
    Type: Application
    Filed: June 11, 2019
    Publication date: December 17, 2020
    Applicant: Intel Corporation
    Inventors: Manish Dubey, Amitesh Saha, Marco Aurelio Cartas, Peng Li, Bamidele Daniel Falola
  • Publication number: 20200381332
    Abstract: Disclosed herein are integrated circuit (IC) packages with solder thermal interface materials (STIMs) with embedded particles, as well as related methods and devices. For example, in some embodiments, an IC package may include a package substrate, a lid, a die between the package substrate and the lid and a STIM between the die and the lid. The STIM may include embedded particles, and at least some of the embedded particles may have a diameter equal to a distance between the die and the lid.
    Type: Application
    Filed: May 28, 2019
    Publication date: December 3, 2020
    Applicant: Intel Corporation
    Inventors: Amitesh Saha, Sergio Antonio Chan Arguedas, Marco Aurelio Cartas, Ken Hackenberg, Peng Li
  • Publication number: 20200373220
    Abstract: Disclosed herein are integrated circuit (IC) packages with thermal interface materials (TIMs) with different material compositions, as well as related methods and devices. For example, in some embodiments, an IC package may include a package substrate, a die, and TIM, wherein the die is between the TIM and the package substrate along a vertical axis. The TIM may include a first TIM having a first material composition and a second TIM having a second material composition; the first material composition may be different than the second material composition, and the first TIM and the second TIM may be in different locations along a lateral axis perpendicular to the vertical axis.
    Type: Application
    Filed: May 22, 2019
    Publication date: November 26, 2020
    Applicant: Intel Corporation
    Inventors: Sergio Antonio Chan Arguedas, Amitesh Saha, Marco Aurelio Cartas, Ken Hackenberg, Emilio Tarango Valles
  • Publication number: 20200185290
    Abstract: Semiconductor packages having a sealant bridge between an integrated heat spreader and a package substrate are described. In an embodiment, a semiconductor package includes a sealant bridge anchoring the integrated heat spreader to the package substrate at locations within an overhang gap laterally between a semiconductor die and a sidewall of the integrated heat spreader. The sealant bridge extends between a top wall of the integrated heat spreader and a die side component, such as a functional electronic component or a non-functional component, or a satellite chip on the package substrate. The sealant bridge modulates warpage or stress in thermal interface material joints to reduce thermal degradation of the semiconductor package.
    Type: Application
    Filed: June 30, 2017
    Publication date: June 11, 2020
    Inventors: Dinesh PADMANABHAN RAMALEKSHMI THANU, Hemanth K. DHAVALESWARAPU, Venkata Suresh GUTHIKONDA, John J. BEATTY, Yonghao AN, Marco Aurelio CARTAS AYALA, Luke J. GARNER, Peng LI
  • Publication number: 20200126887
    Abstract: An apparatus is provided which comprises: a package substrate, an integrated circuit device coupled with contacts on a surface of the package substrate, underfill between the integrated circuit device and the surface of the package substrate, thermal interface material on a surface of the integrated circuit device opposite the package substrate, a heat spreader in contact with the thermal interface material, and a material on a fillet of the underfill, the material adjacent to the thermal interface material. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: October 18, 2018
    Publication date: April 23, 2020
    Applicant: Intel Corporation
    Inventors: Ziyin Lin, Jingyi Huang, Peng Li, Marco Aurelio Cartas, Nisha Ananthakrishnan