Abstract: A power semiconductor device includes: at least one substrate; at least one power semiconductor die arranged over the at least one substrate; a first leadframe arranged over the at least one power semiconductor substrate and over the at least one power semiconductor die, the first leadframe being arranged at least partially in a first plane and including one or more connecting portions extending out of the first plane in a first direction; and a second leadframe at least partially arranged in a second plane above or below the first plane and including one or more attachment sites. The one or more connecting portions extend into the second plane at the one or more attachment sites. The one or more connecting portions are arranged at a non-zero distance from the second leadframe, the non-zero distance being bridged by weld seams at the one or more attachment sites.

Abstract: A power semiconductor module includes: an electrically insulative enclosure; a plurality of power semiconductor dies attached to a substrate inside the electrically insulative enclosure; a lead frame or clip frame disposed above the power semiconductor dies inside the electrically insulative enclosure and electrically connected to the power semiconductor dies; a plurality of contact pins attached to the lead frame or clip frame and protruding through a first side of the electrically insulative enclosure to form an electrical connection interface outside the electrically insulative enclosure; and a plurality of vibration dampeners attached to the lead frame or clip frame. The vibration dampeners protrude through the first side of the electrically insulative enclosure and are separate from the electrical connection interface.

Abstract: A molded power semiconductor module includes: one or more power semiconductor dies; a molded body at least partially encapsulating each power semiconductor die and having opposing first and second sides, and lateral sides connecting the first and second sides; and first and second power contacts arranged laterally next to each other at a first one of the lateral sides of the molded body and electrically coupled to the power semiconductor die(s). The power contacts each have opposing first and second sides, each first side having an exposed part exposed from the molded body, each second side having a part that is arranged in a vertical direction below an outline of the respective exposed part of the first side and that is at least partially covered by a protrusion part of the molded body. The vertical direction is perpendicular to the first and second sides of the power contacts.

Abstract: A molded power semiconductor package includes: at least one first power electronics carrier having a metallization layer disposed on an electrically insulating substrate; a plurality of first power semiconductor dies attached to the metallization layer of the at least one first power electronics carrier; at least one second power electronics carrier having a metallization layer disposed on an electrically insulating substrate; a plurality of second power semiconductor dies attached to the metallization layer of the at least one second power electronics carrier; and a mold compound encasing the plurality of first power semiconductor dies and the plurality of second power semiconductor dies, and at least partly encasing the at least one first power electronics carrier and the at least one second power electronics carrier. The at least one first power electronics carrier and the at least one second power electronics carrier lie in a same plane.

Abstract: A power semiconductor package includes first power semiconductor dies attached to a metallization layer of at least one first power electronics carrier and second power semiconductor dies attached to a metallization layer of at least one second power electronics carrier. A first lead frame includes a first structured metal frame electrically connected to a load terminal of each first power semiconductor die, and a second structured metal frame electrically connected to a load terminal of each second power semiconductor die and to the metallization layer of the first power electronics carrier. A second lead frame above the first lead frame includes first and second leads electrically connected to the metallization layer of the second power electronics carrier, a third lead between the first and second leads and electrically connected to the first structured metal frame, and a fourth lead electrically connected to the second structured metal frame.