Abstract: A power semiconductor device and method for production thereof is specified involving an electrode, a base layer of a first conductivity type provided on the electrode, at least one contact layer provided on the base layer, a gate contact provided on the base layer and on the at least one contact layer, an insulation layer between the gate contact and the base layer and between the at least one contact layer and the gate contact, and at least one zone of a second conductivity type within the base layer, wherein the at least one zone is constructed and arranged to shift away a peak electric field generated in the base layer from the insulation layer between the gate contact and the base layer.

Abstract: A power semiconductor device (1) comprising a semiconductor body (2) extending in a vertical direction between a first main surface (21) and a second main surface (22), a trench (4) extending from the first main surface (21) into the semiconductor body (2) in the vertical direction, and an insulated trench gate electrode (3) that is formed on the first main surface (21) and extends into the trench (4) is specified, wherein the trench (4) is subdivided along a main extension direction of the trench (4) in a plurality of segments (41) and the insulated trench gate electrode (3) continuously extends over the plurality of segments (41).

Abstract: In at least one embodiment, the power semiconductor device (1) comprises a semiconductor body (2), and a protection layer (3) at the semiconductor body (2), wherein the protection layer (3) comprises a material having a surface energy of at most 0.1 mJ/m2, and the protection layer (3) comprises a geometric structuring (33) having a feature size (F) of at least 0.04 ?m and of at most 0.1 mm, seen in top view of the protection layer (3).

Abstract: A power semiconductor device is provided. In an embodiment, the power semiconductor device comprises a source region, a channel region in the semiconductor body, and a gate electrode at the channel region. The gate electrode is electrically insulated from the semiconductor body. The channel region is of a second conductivity type different from the first conductivity type. The channel region comprises a first dopant having an activation energy of at most 0.15 eV, and a second dopant having an activation energy of at least 0.3 eV.

Abstract: A power semiconductor device comprises a drift layer of a first conductivity type, a source layer of the first conductivity type on the drift layer, with an insulated trench gate electrode which extends through the source layer into the drift layer, and an implant layer of a second conductivity type different than the first conductivity type with a homogeneous doping region having a doping variation of at most 8%. The homogeneous doping region is arranged between the source layer and the drift layer and has a homogeneous doping region thickness of at least 150 nm. A method is provided for producing a power semiconductor device with an insulated trench gate electrode.

Abstract: The present invention relates to a method and a system (400) for filling a closed container (200) with a fixative solution. The system comprises a container (200) comprising a container body (230) for receiving a biological specimen, a lid (220) for selectively closing the container body (230) and a port (100) forming a unidirectional barrier in a direction from the inside (IC) to the outside (OC) of the closed container (200). The system further comprises a dispensing apparatus (500) having a filling nozzle (300) for dispensing the fixative solution. The filling nozzle (300) is relatively moveable with respect to the container (200) between a retracted position and a filling position to fill the container (200) with the fixative solution.

Abstract: A silicon carbide (SiC) planar transistor device includes a SiC semiconductor substrate of a first charge type, a SiC epitaxial layer of the first charge type formed at a top surface of the SiC semiconductor substrate, a source structure of the first charge type formed at a top surface of the SiC epitaxial layer, a drain structure of the first charge type formed at a bottom surface of the SiC semiconductor substrate, a gate structure comprising a gate runner and a gate dielectric that covers at least part of the source structure and the gate runner, and a channel region of a second charge type located in vertical direction below the gate structure and adjacent to the source structure. The channel can be formed by performing a plurality of implantation steps so that the channel region comprises a first region and a second region.

Abstract: A joining apparatus for supporting strips of adhesive labels comprises two modules each of which in turn comprises a conveying element of the respective supporting strip; a cutting element configured to cut a respective supporting strip; a joining element that can be configured in a first operating position, in which it keeps in position a respective supporting strip and/or a fixing element, and in a second operating position in which it abuts against the joining element of the other module so as to join the supporting strips; a locking element that can be configured between an active position and a passive position. In particular, at least one joining element can be removed from the respective module to allow the introduction of the fixing element even when the two modules are in the neared configuration to one another. The subject matter of the present patent application is also a joining process for supporting strips of adhesive labels.

Abstract: A silicon carbide transistor device includes a silicon carbide semiconductor and a silicon carbide epitaxial layer formed at a top surface of the substrate. A source structure is formed in a top surface of the silicon carbide epitaxial layer and includes a p-well region, an n-type source region and a p-type contact region. A source contact structure is formed over and electrically connected to a top surface of the source structure. A planar gate structure includes a gate dielectric and a gate runner adjacent a p-type channel region. The gate dielectric covers the channel region, at least part of the source structure and at least part of the source contact structure. The gate runner is electrically insulated from the channel region and the source structure and the source contact structure by the gate dielectric and overlaps the channel region.

Abstract: A silicon carbide power device, e.g., a vertical power MOSFET or an IGBT, includes a silicon carbide wafer. A first stressor and a second stressor are arranged in the silicon carbide wafer at a first main side. A first channel region, a first portion of a drift layer and a second channel region are laterally arranged between the first stressor and the second stressor in a second lateral direction parallel to the first main side and perpendicular to the first lateral direction. A stress can be introduced by the first stressor and the second stressor in the first channel region and in the second channel region.

Abstract: A silicon carbide power device, e.g., a vertical power MOSFET or an IGBT, includes a silicon carbide wafer. A first stressor and a second stressor are arranged in the silicon carbide wafer at a first main side. A first channel region, a first portion of a drift layer and a second channel region are laterally arranged between the first stressor and the second stressor in a second lateral direction parallel to the first main side and perpendicular to the first lateral direction. A stress can be introduced by the first stressor and the second stressor in the first channel region and in the second channel region.

Abstract: The present invention relates to a method and a system (400) for filling a closed container (200) with a fixative solution. The system comprises a container (200) comprising a container body (230) for receiving a biological specimen, a lid (220) for selectively closing the container body (230) and a port (100) forming a unidirectional barrier in a direction from the inside (IC) to the outside (OC) of the closed container (200). The system further comprises a dispensing apparatus (500) having a filling nozzle (300) for dispensing the fixative solution. The filling nozzle (300) is relatively moveable with respect to the container (200) between a retracted position and a filling position to fill the container (200) with the fixative solution.

Abstract: The present invention relates to a method and a system (400) for filling a closed container (200) with a fixative solution. The system comprises a container (200) comprising a container body (230) for receiving a biological specimen, a lid (220) for selectively closing the container body (230) and a port (100) forming a unidirectional barrier in a direction from the inside (IC) to the outside (OC) of the closed container (200). The system further comprises a dispensing apparatus (500) having a filling nozzle (300) for dispensing the fixative solution. The filling nozzle (300) is relatively moveable with respect to the container (200) between a retracted position and a filling position to fill the container (200) with the fixative solution.

Abstract: A power semiconductor module including at least one power semiconductor chip providing a power electronics switch; and a semiconductor wafer, to which the at least one power semiconductor chip is bonded; wherein the semiconductor wafer is doped, such that it includes a field blocking region and an electrically conducting region on the field blocking region, to which electrically conducting region the at least one power semiconductor chip is bonded.

Abstract: A power semiconductor device includes a semiconductor wafer having a first main side surface and a second main side surface. The semiconductor wafer includes a first semiconductor layer having a first conductivity type and a plurality of columnar or plate-shaped first semiconductor regions extending in the first semiconductor layer between the first main side surface and the second main side surface in a vertical direction perpendicular to the first main side surface and the second main side surface. The first semiconductor regions have a second conductivity type, which is different from the first conductivity type. Therein, the first semiconductor is a layer of hexagonal silicon carbide. The first semiconductor regions are regions of 3C polytype silicon carbide.

Abstract: The present invention relates to a system (100) for medical gross examination. The system (100) comprises an examination area (200) for receiving biospecimens (TS), a camera device (300) for visual inspection of the examination area (200) and for providing images captured during visual inspection, and a display device (400) for displaying the captured images. The system (100) further comprises an eye-tracking device (500) for detecting eye information based on the point of gaze (505) or eye movement of a user's (OP) eye and a controller (600) for controlling the system (100) based on the detected eye information. Furthermore, the invention relates to a method for the control of a system (100) for medical gross examination, comprising the steps of placing a biospecimen (TS) in an examination area (200), visually inspecting the examination area (200), capturing images thereof and displaying the captured images.

Abstract: The present invention relates to a method and a system (400) for filling a closed container (200) with a fixative solution. The system comprises a container (200) comprising a container body (230) for receiving a biological specimen, a lid (220) for selectively closing the container body (230) and a port (100) forming a unidirectional barrier in a direction from the inside (IC) to the outside (OC) of the closed container (200). The system further comprises a dispensing apparatus (500) having a filling nozzle (300) for dispensing the fixative solution. The filling nozzle (300) is relatively moveable with respect to the container (200) between a retracted position and a filling position to fill the container (200) with the fixative solution.

Abstract: In a power semiconductor device of the application a total number n of floating field rings (10_1 to 10_n) formed in a termination area is at least 10. For any integer i in a range from i=2 to i=n, a ring-to-ring separation di,i?i between an i-th floating field ring and a directly adjacent (i?1)-th floating field ring, when counting the floating field rings (10_1 to 10_n) along a straight line starting from a main pn-junction and extending in a lateral direction away from the main pn-junction, is given by the following formula: di,i?1=d1,0+?j=1j=i?1 ?j for i=2 to n, wherein d1,0 is a distance between the innermost floating field ring (10_1) closest to the main pn-junction and the main pn-junction, and wherein: ?zone1?0.05·?zone2<?j<?zone1+0.05·?zone2 for j=1 to I?2, 2·?zone2<|?j|<10·?zone2. for j=I?1, 0.95·?zone2<?j<1.05·?zone2 for j=I to n?1, ?zone2>0.1 ?m, and ??zone2/2<?zone1<?zone2/2, wherein I is an integer, for which 3?l?n/2.

Abstract: A power semiconductor device includes a semiconductor wafer having a first main side surface and a second main side surface. The semiconductor wafer includes a first semiconductor layer having a first conductivity type and a plurality of columnar or plate-shaped first semiconductor regions extending in the first semiconductor layer between the first main side surface and the second main side surface in a vertical direction perpendicular to the first main side surface and the second main side surface. The first semiconductor regions have a second conductivity type, which is different from the first conductivity type. Therein, the first semiconductor is a layer of hexagonal silicon carbide. The first semiconductor regions are regions of 3C polytype silicon carbide.

Abstract: In a power semiconductor device of the application a total number n of floating field rings (10_1 to 10_n) formed in a termination area is at least 10. For any integer i in a range from i=2 to i=n, a ring-to-ring separation di,1?i between an i-th floating field ring and a directly adjacent (i?1)-th floating field ring, when counting the floating field rings (10_1 to 10_n) along a straight line starting from a main pn-junction and extending in a lateral direction away from the main pn-junction, is given by the following formula: di,i?1=d1,0+?j=1j=i?1 ?j for i=2 to n, wherein d1,0 is a distance between the innermost floating field ring (10_1) closest to the main pn-junction and the main pn-junction, and wherein: ?zone1?0.05·?zone2<?j<?zone1+0.05·?zone2 for j=1 to I-2, 2·?zone2<zone2<Aj<Azonel +0.05 A zone2 <|?j|<10·?zone2. for j=I?1, 0.95·?zone2<?j<1.05·?zone2 for j=I to n?1, ?zone2<0.1 ?m, and ??zone2/2 <?zone1<?zone2/2 , wherein I is an integer, for which 3?l?n/2.