Patents by Inventor Marco Brambilla
Marco Brambilla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11474970Abstract: The disclosure describes techniques for interrupt and inter-processor communication (IPC) mechanisms that are shared among computer processors. For example, an artificial reality system includes a plurality of processors; an inter-processor communication (IPC) unit comprising a register, wherein the IPC unit is configured to: receive a memory access request from a first processor of the processors, wherein the memory access request includes information indicative of a hardware identifier (HWID) associated with the first processor; determine whether the HWID associated with the first processor matches an HWID for the register of the IPC unit; and permit, based on determining that the HWID associated with the first processor matches the HWID for the register of the IPC unit, the memory access request to indicate a communication from the first processor to at least one other processor.Type: GrantFiled: December 24, 2019Date of Patent: October 18, 2022Assignee: Meta Platforms Technologies, LLCInventors: Jun Wang, Neeraj Upasani, Wojciech Stefan Powiertowski, Drew Eric Wingard, Gregory Edward Ehmann, Marco Brambilla, Minli Lin, Miguel Angel Guerrero
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Patent number: 11423152Abstract: In general, this disclosure describes techniques for using a random number generator to affect the lengths of clock cycles in a clock waveform that drives the timing of operations performed by processing circuitry. In one example, the processing circuitry includes a central processing unit and a clock generator. The clock generator is configured, upon receiving an indication of a boot command for the processing circuitry, generate a random number using a true random number generator and generate, based at least in part on the random number, an output clock waveform indicating at least a length of a clock cycle for the central processing unit. The central processing unit is configured to execute a boot sequence for at least the processing circuitry using the output clock waveform.Type: GrantFiled: August 13, 2019Date of Patent: August 23, 2022Assignee: Facebook Technologies, LLCInventors: Marco Brambilla, Jay Tsao, Neeraj Upasani
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Publication number: 20210089366Abstract: The disclosure describes techniques for interrupt and inter-processor communication (IPC) mechanisms that are shared among computer processors. For example, an artificial reality system includes a plurality of processors; an inter-processor communication (IPC) unit comprising a register, wherein the IPC unit is configured to: receive a memory access request from a first processor of the processors, wherein the memory access request includes information indicative of a hardware identifier (HWID) associated with the first processor; determine whether the HWID associated with the first processor matches an HWID for the register of the IPC unit; and permit, based on determining that the HWID associated with the first processor matches the HWID for the register of the IPC unit, the memory access request to indicate a communication from the first processor to at least one other processor.Type: ApplicationFiled: December 24, 2019Publication date: March 25, 2021Inventors: Jun Wang, Neeraj Upasani, Wojciech Stefan Powiertowski, Drew Eric Wingard, Gregory Edward Ehmann, Marco Brambilla, Minli Lin, Miguel Angel Guerrero
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Publication number: 20200394306Abstract: In general, this disclosure describes techniques for using a random number generator to affect the lengths of clock cycles in a clock waveform that drives the timing of operations performed by processing circuitry. In one example, the processing circuitry includes a central processing unit and a clock generator. The clock generator is configured, upon receiving an indication of a boot command for the processing circuitry, generate a random number using a true random number generator and generate, based at least in part on the random number, an output clock waveform indicating at least a length of a clock cycle for the central processing unit. The central processing unit is configured to execute a boot sequence for at least the processing circuitry using the output clock waveform.Type: ApplicationFiled: August 13, 2019Publication date: December 17, 2020Inventors: Marco Brambilla, Jay Tsao, Neeraj Upasani
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Patent number: 9323633Abstract: A dual-master controller includes a plurality of JTAG data registers including a controller-mode register that stores information indicating a standard JTAG or a processor-controlled mode of operation. A JTAG TAP controller receives control signals over a standard test access port and a processor controller receives processor control signals over an external processor bus. A selection multiplexer outputs either signals on the standard JTAG access port or the external processor bus responsive to a JTAG mode selection signal. A logic circuit activates the JTAG mode selection signal responsive to the force JTAG signal being active or information in the controller-mode register indicating the standard JTAG mode, and deactivates the JTAG mode selection signal responsive to the force JTAG signal being deactivated or the information in the controller-mode register indicating the processor-controller mode.Type: GrantFiled: March 28, 2013Date of Patent: April 26, 2016Assignee: STMicroelectronics, Inc.Inventors: Marco Brambilla, Ulderic Lacour, Cecilia Ozdemir
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Publication number: 20140298122Abstract: A dual-master controller includes a plurality of JTAG data registers including a controller-mode register that stores information indicating a standard JTAG or a processor-controlled mode of operation. A JTAG TAP controller receives control signals over a standard test access port and a processor controller receives processor control signals over an external processor bus. A selection multiplexer outputs either signals on the standard JTAG access port or the external processor bus responsive to a JTAG mode selection signal. A logic circuit activates the JTAG mode selection signal responsive to the force JTAG signal being active or information in the controller-mode register indicating the standard JTAG mode, and deactivates the JTAG mode selection signal responsive to the force JTAG signal being deactivated or the information in the controller-mode register indicating the processor-controller mode.Type: ApplicationFiled: March 28, 2013Publication date: October 2, 2014Applicant: STMicroelectronics, Inc.Inventors: MARCO BRAMBILLA, ULDERIC LACOUR, CECILIA OZDEMIR
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Patent number: 8825701Abstract: A computer-implemented method of management of queries for crowd searching is presented. In the method, an input model including input data e structured queries using query operators is mapped into an output model, which is obtained by modifying the input data and by adding the answers to the structured queries. Input data comprise at least one search object, which may be imported from a search system, at least one structured query operator corresponding to social interactions and a human-generated question related to the at least one search object. Mapping of the input model is according to a query task execution plan that defines a query task to be solved by a crowd, wherein mapping comprises selecting at least one social search engine running on a respective social platform and selecting one or more groups of responders interacting with the at least one social search engines and targeted to respond to the query task.Type: GrantFiled: July 16, 2012Date of Patent: September 2, 2014Assignee: Politecnico di MilanoInventors: Stefano Ceri, Marco Brambilla, Alessandro Bozzon
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Publication number: 20140019435Abstract: A computer-implemented method of management of queries for crowd searching is presented. In the method, an input model including input data e structured queries using query operators is mapped into an output model, which is obtained by modifying the input data and by adding the answers to the structured queries. Input data comprise at least one search object, which may be imported from a search system, at least one structured query operator corresponding to social interactions and a human-generated question related to the at least one search object. Mapping of the input model is according to a query task execution plan that defines a query task to be solved by a crowd, wherein mapping comprises selecting at least one social search engine running on a respective social platform and selecting one or more groups of responders interacting with the at least one social search engines and targeted to respond to the query task.Type: ApplicationFiled: July 16, 2012Publication date: January 16, 2014Applicant: POLITECNICO DI MILANOInventors: Stefano CERI, Marco Brambilla, Alessandro Bozzon
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Patent number: 8180768Abstract: A method and a computer program product for identifying the domains, selecting for each domain one domain-specific search engine and data source to be involved, generating the domain-specific subqueries for each selected search engine, defining a strategy for sending requests to each search engine and data source, and receiving, merging and ranking results. The result of the multi-domain query is a list of combinations, where every combination consists of a tuple of data, each relative to one of the domains of the query; such data is present in the results returned either by search engines or by data sources. The method provides the combinations having the highest combination score, as computed by a monotone aggregation function over the combinations.Type: GrantFiled: August 13, 2009Date of Patent: May 15, 2012Assignee: Politecnico Di MilanoInventors: Stefano Ceri, Daniele Braga, Marco Brambilla, Alessandro Campi, Emanuele Della Valle, Piero Fraternali, Davide Martinenghi, Marco Tagliasacchi
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Publication number: 20110040749Abstract: A method and a computer program product for identifying the domains, selecting for each domain one domain-specific search engine and data source to be involved, generating the domain-specific subqueries for each selected search engine, defining a strategy for sending requests to each search engine and data source, and receiving, merging and ranking results. The result of the multi-domain query is a list of combinations, where every combination consists of a tuple of data, each relative to one of the domains of the query; such data is present in the results returned either by search engines or by data sources. The method provides the combinations having the highest combination score, as computed by a monotone aggregation function over the combinations.Type: ApplicationFiled: August 13, 2009Publication date: February 17, 2011Applicant: POLITECNICO DI MILANOInventors: Stefano Ceri, Daniele Braga, Marco Brambilla, Alessandro Campi, Emanuele Della Valle, Piero Fraternali, Davide Martinenghi, Marco Tagliasacchi
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Patent number: 4110595Abstract: An array of adjacent wave guides feed high-frequency energy into a vacuum chamber in which a toroidal plasma is confined by a magnetic field, the wave guide array being located between two toroidal current windings. Waves are excited in the wave guide at a frequency substantially equal to the lower frequency hybrid wave of the plasma and a substantially equal phase shift is provided from one guide to the next between the waves therein. For plasmas of low peripheral density gradient, the guides are excited in the TE.sub.01 mode and the output electric field is parallel to the direction of the toroidal magnetic field. For exciting waves in plasmas of high peripheral density gradient, the guides are excited in the TM.sub.01 mode and the magnetic field at the wave guide outlets is parallel to the direction of the toroidal magnetic field.Type: GrantFiled: June 19, 1975Date of Patent: August 29, 1978Assignee: The United States of America as represented by the United States Department of EnergyInventors: Marco Brambilla, Pascal Lallia