Abstract: This disclosure provides a method to realize a hardware device, in particular a hardware device configured on a FPGA or manufactured as an ASIC, configured to meet maximum performances achievable by a certain algorithm defined by a high-level software code. The method is based on the steps of translating of the high-level software code into a corresponding low-level software code defining low-level operation, for executing the same operations defined by the high-level software code; then on estimating of certain parameters to calculate a peak performance value P and memory transfer performance Pm of the hardware device; finally, on realizing the hardware device with hardware resources having performance within the peak performance value P and memory transfer performance Pm.

Abstract: This disclosure provides a method to realize a hardware device, in particular a hardware device configured on a FPGA or manufactured as an ASIC, configured to meet maximum performances achievable by a certain algorithm defined by a high-level software code. The method is based on the steps of translating of the high-level software code into a corresponding low-level software code defining low-level operation, for executing the same operations defined by the high-level software code; then on estimating of certain parameters to calculate a peak performance value P and memory transfer performance Pm of the hardware device; finally, on realizing the hardware device with hardware resources having performance within the peak performance value P and memory transfer performance Pm.

Abstract: A method of aligning a first string (read) of characters representing genomic data to a second string (contig) of characters representing genomic data, using at least a Finite State Machine having a storage memory, is disclosed. Substantially, data representing at least a first string of characters representing genomic data (read) and at least a second string of characters representing genomic data (contig) are loaded into a storage memory and a first block of characters of the read and a second block of characters of the contig are selected, wherein the two blocks have the same number of characters and are identified respectively by a first index and by a second index pointing to start positions of the two blocks. Then the two blocks of characters are compared and the two indexes are updated at each cycle of the Finite State Machine until all blocks of characters of the read have been compared. It is also disclosed a hardware device, preferably a FPGA, configured for executing the disclosed method.

Abstract: A power optimization system and method for virtualized environments at least comprising a domain layer on which a plurality of virtual machines are implemented, a hardware layer and hypervisor layer configured for abstracting between the virtual machines of the domain layer and the hardware layer, wherein the system comprises a hardware interface to set a limit on the power consumption of at least one processing means implemented in a hardware layer and a software structure for performing an optimization of the available resource allocations for the running workload in terms of power consumption, wherein the software structure is an Observe-Decide-Act control loop structure, comprising an observe stage, a decide stage and an act stage, and wherein the observe stage interfaces with means configured for reading performance values inside at least one model specific register of the at least one processing means.