Patents by Inventor Marco Ferrario
Marco Ferrario has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9558799Abstract: A memory device includes an operation having a phase to provide an upper row address from a row address buffer, a phase to combine the upper row address with a lower row address to select data for a row data buffer, and a phase to output the data from the row data buffer, wherein an activate command starts and following activate commands are ignored until a preset time has elapsed.Type: GrantFiled: November 30, 2015Date of Patent: January 31, 2017Assignee: Micron Technology, Inc.Inventors: Marco Ferrario, Christophe Vincent Antoine Laurent, Francesco Mastroianni
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Publication number: 20160086662Abstract: A memory device includes an operation having a phase to provide an upper row address from a row address buffer, a phase to combine the upper row address with a lower row address to select data for a row data buffer, and a phase to output the data from the row data buffer, wherein an activate command starts and following activate commands are ignored until a preset time has elapsed.Type: ApplicationFiled: November 30, 2015Publication date: March 24, 2016Inventors: Marco Ferrario, Christophe Vincent Antoine Laurent, Francesco Mastroianni
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Patent number: 9208835Abstract: A phase-change memory includes a phase to provide an upper row address from a row address buffer, a phase to combine the upper row address with a lower row address to select data for a row data buffer, and a phase to output the data from the row data buffer, where an activate command starts and following activate commands are ignored until a preset time has elapsed.Type: GrantFiled: December 29, 2009Date of Patent: December 8, 2015Assignee: Micron Technology, Inc.Inventors: Marco Ferrario, Christophe Vincent Antoine Laurent, Francesco Mastroianni
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Patent number: 8832392Abstract: Example embodiments of a non-volatile memory device may comprise receiving an index value at one or more input terminals of a memory device and storing the index value in a first register of the memory device. The first register may be implemented in a first clock domain, and the index value may identify a second register of the memory device implemented in a second clock domain.Type: GrantFiled: September 13, 2013Date of Patent: September 9, 2014Assignee: Micron Technology, Inc.Inventors: Marco Ferrario, Daniele Balluchi
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Publication number: 20140019702Abstract: Example embodiments of a non-volatile memory device may comprise receiving an index value at one or more input terminals of a memory device and storing the index value in a first register of the memory device. The first register may be implemented in a first clock domain, and the index value may identify a second register of the memory device implemented in a second clock domain.Type: ApplicationFiled: September 13, 2013Publication date: January 16, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Marco Ferrario, Daniele Balluchi
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Patent number: 8539189Abstract: Example embodiments of a non-volatile memory device may comprise receiving an index value at one or more input terminals of a memory device and storing the index value in a first register of the memory device. The first register may be implemented in a first clock domain, and the index value may identify a second register of the memory device implemented in a second clock domain.Type: GrantFiled: October 29, 2010Date of Patent: September 17, 2013Assignee: Micron Technology, Inc.Inventors: Marco Ferrario, Daniele Balluchi
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Publication number: 20130077393Abstract: A Phase-Change Memory (PCM) that allows an Activate command to start and all following Activate commands are ignored until a time tRC has elapsed.Type: ApplicationFiled: December 29, 2009Publication date: March 28, 2013Inventors: Marco Ferrario, Christophe Vincent Antoine Laurent, Francesco Mastroianni
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Publication number: 20120137093Abstract: Example embodiments described herein may relate to performing reliable right commands for non-volatile memory devices.Type: ApplicationFiled: November 30, 2010Publication date: May 31, 2012Applicant: Micron Technology, Inc.Inventors: Marco Ferrario, Emanuele Confalonieri, Danilo Caraccio
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Publication number: 20110271038Abstract: Example embodiments of a non-volatile memory device may comprise receiving an index value at one or more input terminals of a memory device and storing the index value in a first register of the memory device. The first register may be implemented in a first clock domain, and the index value may identify a second register of the memory device implemented in a second clock domain.Type: ApplicationFiled: October 29, 2010Publication date: November 3, 2011Applicant: Micron Technology, Inc.Inventors: Marco Ferrario, Daniele Balluchi
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Patent number: 7596023Abstract: A memory device may include an array of addressable three-level cells, a coding circuit being input with three-bit strings and generating corresponding ternary strings based upon a code, and a program circuit being input with the ternary strings and storing them in respective pairs of three-level cells. The memory device also may include a read circuit reading stored ternary strings in the respective pairs of three-level cells, and a decoding circuit being input with the stored ternary strings and generating corresponding strings of three bits based upon the code.Type: GrantFiled: November 2, 2007Date of Patent: September 29, 2009Inventors: Alessandro Magnavacca, Massimiliano Scotti, Nicola Del Gatto, Claudio Nava, Marco Ferrario, Massimiliano Mollichelli
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Patent number: 7445075Abstract: A four-wheeled vehicle includes a steering mechanism having a bar handle, right and left front wheels, and right and left rear wheels. The vehicle includes a front cover and a windshield disposed in front of the bar handle. The vehicle includes a driver's seat, and a rear passenger seat disposed behind the driver's seat and between the rear wheels. The rear passenger seat is directed forwardly. The vehicle includes a power unit part disposed below the rear passenger seat, and a body cover disposed rearwardly of the driver's seat.Type: GrantFiled: July 29, 2003Date of Patent: November 4, 2008Assignee: Honda Giken Kogyo Kabushiki KaishaInventors: Eiji Ozawa, Oumi Iida, Seiji Higashihara, Yumio Shibata, Koichi Sugioka, Kiyotaka Fujiwara, Paolo Allasia, Marco Ferrario, Raffaele Vergano, Andreas Wachtler
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Publication number: 20080106937Abstract: A memory device may include an array of addressable three-level cells, a coding circuit being input with three-bit strings and generating corresponding ternary strings based upon a code, and a program circuit being input with the ternary strings and storing them in respective pairs of three-level cells. The memory device also may include a read circuit reading stored ternary strings in the respective pairs of three-level cells, and a decoding circuit being input with the stored ternary strings and generating corresponding strings of three bits based upon the code.Type: ApplicationFiled: November 2, 2007Publication date: May 8, 2008Applicant: STMicroelectronics S.r.I.Inventors: Alessandro MAGNAVACCA, Massimiliano Scotti, Nicola Del Gatto, Claudio Nava, Marco Ferrario, Massimiliano Mollichelli
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Patent number: 7359246Abstract: A memory device includes a plurality of memory cells each one for storing a value, at least one reference cell, biasing means for biasing a set of selected memory cells and the at least one reference cell with a biasing voltage having a substantially monotone time pattern, means for detecting the reaching of a threshold value by a current of each selected memory cell and of each reference cell, and means for determining the value stored in each selected memory cell according to a temporal relation of the reaching of the threshold value by the currents of the selected memory cell and of the at least one reference cell. The biasing means includes means for applying a controlled biasing current to the selected memory cells and to the at least one reference cell.Type: GrantFiled: January 26, 2006Date of Patent: April 15, 2008Assignee: STMicroelectronics S.r.l.Inventors: Marco Sforzin, Nicola Del Gatto, Marco Ferrario, Emanuele Confalonieri
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Patent number: 7317637Abstract: A method and circuit for programming a multilevel memory of a flash EEPROM type having a matrix of cells grouped in memory words. The method provides for the simultaneous generation of a first programming voltage value and a second verify voltage value to bias word lines of the memory matrix during programming and verify operations, respectively, of the memory itself. A circuit implementing the above method is also provided.Type: GrantFiled: October 27, 2005Date of Patent: January 8, 2008Assignee: STMicroelectronics S.r.l.Inventors: Emanuele Confalonieri, Nicola Del Gatto, Carlo Lisi, Marco Ferrario
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Publication number: 20060198187Abstract: A memory device includes a plurality of memory cells each one for storing a value, at least one reference cell, biasing means for biasing a set of selected memory cells and the at least one reference cell with a biasing voltage having a substantially monotone time pattern, means for detecting the reaching of a threshold value by a current of each selected memory cell and of each reference cell, and means for determining the value stored in each selected memory cell according to a temporal relation of the reaching of the threshold value by the currents of the selected memory cell and of the at least one reference cell. The biasing means includes means for applying a controlled biasing current to the selected memory cells and to the at least one reference cell.Type: ApplicationFiled: January 26, 2006Publication date: September 7, 2006Applicant: STMicroelectronics S.r.l.Inventors: Marco Sforzin, Nicola Del Gatto, Marco Ferrario, Emanuele Confalonieri
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Publication number: 20060120161Abstract: A method and circuit for programming a multilevel memory of a flash EEPROM type having a matrix of cells grouped in memory words. The method provides for the simultaneous generation of a first programming voltage value and a second verify voltage value to bias word lines of the memory matrix during programming and verify operations, respectively, of the memory itself. A circuit implementing the above method is also provided.Type: ApplicationFiled: October 27, 2005Publication date: June 8, 2006Applicant: STMicroelectronics S.r.I.Inventors: Emanuele Confalonieri, Nicola Del Gatto, Carlo Lisi, Marco Ferrario
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Patent number: 6956787Abstract: A device for timing random reading of a memory device with a data access time, in which reading is performed by a succession of consecutive operations, the timing device being designed to generate, for each operation, a corresponding timing signal such as to cause, whatever the operating condition of the memory device, the corresponding operation to last for a time equal to a respective fixed duration, which is determined so as to guarantee completion of the operation in the worst operating condition of the memory device within the fixed duration; the sum of the fixed durations being equal to the data access time of the memory device.Type: GrantFiled: November 3, 2003Date of Patent: October 18, 2005Assignee: STMicroelectronics S.r.l.Inventors: Carlo Lisi, Marco Ferrario, Massimiliano Scotti, Emanuele Confalonieri
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Publication number: 20040151035Abstract: A device for timing random reading of a memory device with a data access time, in which reading is performed by a succession of consecutive operations, the timing device being designed to generate, for each operation, a corresponding timing signal such as to cause, whatever the operating condition of the memory device, the corresponding operation to last for a time equal to a respective fixed duration, which is determined so as to guarantee completion of the operation in the worst operating condition of the memory device within the fixed duration; the sum of the fixed durations being equal to the data access time of the memory device.Type: ApplicationFiled: November 3, 2003Publication date: August 5, 2004Inventors: Carlo Lisi, Marco Ferrario, Massimiliano Scotti, Emanuele Confalonieri
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Publication number: 20040079561Abstract: A four-wheeled vehicle includes a steering mechanism having a bar handle, right and left front wheels, and right and left rear wheels. The vehicle includes a front cover and a windshield disposed in front of the bar handle. The vehicle includes a driver's seat, and a rear passenger seat disposed behind the driver's seat and between the rear wheels. The rear passenger seat is directed forwardly. The vehicle includes a power unit part disposed below the rear passenger seat, and a body cover disposed rearwardly of the driver's seat.Type: ApplicationFiled: July 29, 2003Publication date: April 29, 2004Applicant: HONDA GIKEN KOGYO KABUSHIKI KAISHAInventors: Eiji Ozawa, Oumi Iida, Seiji Higashihara, Yumio Shibata, Koichi Sugioka, Kiyotaka Fujiwara, Paolo Allasia, Marco Ferrario, Raffaele Vergano, Andreas Wachtler