Patents by Inventor Marco G. Mastrapasqua

Marco G. Mastrapasqua has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7820517
    Abstract: In a metal-oxide semiconductor device including first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, a drift region formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions, an insulating layer formed on at least a portion of the upper surface of the semiconductor layer, and a gate formed on the insulating layer and at least partially between the first and second source/drain regions, a method for controlling an amount of hot carrier injection degradation in the device includes the steps of: forming a shielding structure on the insulating layer above at least a portion of the drift region and substantially between the gate and the second source/drain region; and adjusting an amount of coverage of the shielding structure over an upper surface of the drift region so as to minimiz
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: October 26, 2010
    Assignee: Agere Systems Inc.
    Inventors: Peter L. Gammel, Isik C. Kizilyalli, Marco G. Mastrapasqua, Muhammed Ayman Shibib, Zhijian Xie, Shuming Xu
  • Patent number: 7279744
    Abstract: An MOS device is formed including a semiconductor layer of a first conductivity type, and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A drift region is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. An insulating layer is formed on at least a portion of the upper surface of the semiconductor layer and above at least a portion of the drift region. A gate is formed on the insulating layer and at least partially between the first and second source/drain regions. The MOS device further includes a shielding structure formed on the insulating layer above at least a portion of the drift region.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: October 9, 2007
    Assignee: Agere Systems Inc.
    Inventors: Peter L. Gammel, Isik C. Kizilyalli, Marco G. Mastrapasqua, Muhammed Ayman Shibib, Zhijian Xie, Shuming Xu