Abstract: In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include at least one memory cell, a read circuit configured to read the memory cell, wherein the read circuit includes an output holding circuit configured to hold a memory cell content signal read from the memory cell, and an enable circuit configured to provide the memory cell content signal at an output of the read circuit only in case the memory cell fulfills a predefined criterion.

Abstract: In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include at least one memory cell, a read circuit configured to read the memory cell, wherein the read circuit includes an output holding circuit configured to hold a memory cell content signal read from the memory cell, and an enable circuit configured to provide the memory cell content signal at an output of the read circuit only in case the memory cell fulfills a predefined criterion.

Abstract: A memory device architecture having improved bitline pre-charge and wordline timing operations includes a pre-charge driver, a pre-charge line, a timing controller, a wordline driver, and a wordline coupled to a selected memory cell. The pre-charge driver is operable to supply a pre-charge signal to a pre-charge line when activated by the pre-charge triggering signal. The pre-charge line is operable to supply a pre-charge output signal. The timing controller is coupled to receive the pre-charge output signal, and based thereon, provide a wordline triggering signal. The wordline triggering signal is supplied to the wordline driver, which applies a wordline signal to the selected memory cell.

Abstract: A memory device is presented that includes a plurality of memory cells coupled to a bitline, and two or more pre-charging circuits coupled to the bitline. Each of the pre-charging circuits is operable to supply a pre-charge voltage to the bitline, thereby reducing the effective R-C time constant of the bitline compared with the conventional approach in which only a single pre-charging circuit is employed.

Abstract: A memory device architecture having improved bitline pre-charge and wordline timing operations includes a pre-charge driver, a pre-charge line, a timing controller, a wordline driver, and a wordline coupled to a selected memory cell. The pre-charge driver is operable to supply a pre-charge signal to a pre-charge line when activated by the pre-charge triggering signal. The pre-charge line is operable to supply a pre-charge output signal. The timing controller is coupled to receive the pre-charge output signal, and based thereon, provide a wordline triggering signal. The wordline triggering signal is supplied to the wordline driver, which applies a wordline signal to the selected memory cell.

Abstract: A device limits a capacitance charging current. The device has a differentiating device that is coupled in parallel with a capacitance that is to be charged at a charging node. A switching device is connected to an output of the differentiating device. The switching device prevents a charging current—which is supplied to the capacitor—if a predetermined value is applied to the output of the differentiating device.

Abstract: A method for sensing current conducted through a memory cell in which a memory cell current is supplied to, or drawn from, a first sensing node. The first sensing node is defined by a common connection point between the first terminal of a sensor element and an input of an inverting amplifier. A second sensing node is defined by a common connection point between a second terminal of the sensor element and the output of the inverting amplifier. The method further includes applying a reference potential to a reference input of the inverting amplifier, wherein the inverting amplifier is operable to apply substantially the reference potential to the first sensing node and to produce, in response, a sensor signal at the second sensing node, the sensor signal representative of the memory cell current supplied to, or drawn from, the first sensing node. Subsequently, the sensor signal is detected, and accordingly, the memory cell current supplied to, or drawn from the first sensing node can be ascertained.