Abstract: Techniques and articles of manufacture are provided comprising computer readable programs that, when executed on the computer, cause the computer to delete a leaf from a patricia tree having leaf keys and pattern search control blocks containing a prefix and either an end-of-trail leaf or a pointer to another of the pattern search control blocks, by placing each of the prefixes in a tree prefix table; searching for a key in the tree; searching for the key in the prefix table if the tree searching does not find the key in the tree; confirming that the key is deleted if the key is not found in the prefix table; deleting the key from one of the pattern search control blocks; and collapsing the patricia tree by eliminating the left most pattern search control block from the patricia tree if the patricia tree searching finds the key.

Abstract: Method for compressing search tree structures used in rule classification is provided. The method includes classifying packets based on filter rules, compressing a tree structure comprising multiple levels of single bit test nodes and leaf nodes, storing the compressed tree structure in a first memory structure of a storage such that the multiple levels of single bit test nodes and leaf nodes can be accessed from the first memory structure through a single memory access of the storage, collecting single bit test nodes of the tree structure that are in a lowest level of the tree structure, storing only the collected single bit test nodes within a second memory structure of the storage that is contiguous to the first memory structure, collecting leaf nodes of the tree structure, and storing only the collected leaf nodes within a third memory structure of the storage that is contiguous to second memory structure.

Abstract: A method and system for identifying a data structure associated with a packet of data. A processor internal to a packet processor may extract one or more fields in a packet header field of a received packet of data to generate a search key. The internal processor may then be configured to select which table, e.g., routing table, quality of service table, filter table, needs to be accessed using the search key in order to process the received packet of data. A determination may then be made by the internal processor as to whether a CAM or a hash table and a Patricia Tree are used to identify the data structure associated with the received packet of data. Based on table definitions in a register, the internal processor may make such a determination.

Abstract: A method and system for transmitting packets in a packet switching network. Packets received by a packet processor may be prioritized based on the urgency to process them. Packets that are urgent to be processed may be referred to as real-time packets. Packets that are not urgent to be processed may be referred to as non-real-time packets. Real-time packets have a higher priority to be processed than non-real-time packets. A real-time packet may either be discarded or transmitted into a real-time queue based upon its value priority, the minimum and maximum rates for that value priority and the current real-time queue congestion conditions. A non-real-time packet may either be discarded or transmitted into a non-real-time queue based upon its value priority, the minimum and maximum rates for that value priority and the current real-time and non-real-time queue congestion conditions.

Abstract: A method and system for transmitting packets in a packet switching network. Packets received by a packet processor may be prioritized based on the urgency to process them. Packets that are urgent to be processed may be referred to as real-time packets. Packets that are not urgent to be processed may be referred to as non-real-time packets. Real-time packets have a higher priority to be processed than non-real-time packets. A real-time packet may either be discarded or transmitted into a real-time queue based upon its value priority, the minimum and maximum rates for that value priority and the current real-time queue congestion conditions. A non-real-time packet may either be discarded or transmitted into a non-real-time queue based upon its value priority, the minimum and maximum rates for that value priority and the current real-time and non-real-time queue congestion conditions.

Abstract: A procedure is used to provide data structures that handle large numbers of active data entries and a high rate of additions and deletions of active entries. The procedure utilizes one or more of the following modifications. Timers are removed from individual session table entries and are linked via pointers. Bilateral links are established between the session table and the timer structure. Aging/timer checks are applied to the timer control block (TCB). A chain of TCBs, optionally including an excess of blocks, may be used along with packing of multiple TCBs into a single memory location. This excess of blocks permits a terminated session to continue to occupy a TCB until the timer process progresses to that block location in the chain of blocks.

Abstract: An integrated circuit having an array of programmable processing elements and a memory interface linked by an on-chip communication network. Each processing element includes a plurality of processing cores and a local memory. The memory interface block is operably coupled to external memory and to the on-chip communication network. The memory interface supports accessing the external memory in response to messages communicated from the processing elements of the array over the on-chip communication network. A portion of the local memory for a plurality of the processing elements of the array as well as a portion of the external memory are both allocated to store data shared by a plurality of processing elements of the array during execution of programmed operations distributed thereon.

Abstract: An integrated circuit an array of nodes linked by an on-chip communication network. Messages are communicated between nodes utilizing logical channels representing hardware resources at the associated nodes. A given logical channel is associated with a receiver node and a transmitter node. The receiver node is adapted to send flow control messages to the transmitter node. The flow control messages include credits that identify hardware resources of the receiver node that are available for receiving messages over the given logical channel. The transmitter node is adapted to maintain a running total of the credits included as part of the flow control messages communicated from the receiver node and to initiate transmission of messages to the receiver node in accordance with the running total of credits maintained at the transmitter node.

Abstract: An integrated circuit with an array of nodes linked by an on-chip communication network. Messages are communicated between nodes utilizing logical channels representing hardware resources at the associated nodes. A given logical channel is associated with a receiver node and a transmitter node. A set of logical channels are associated with a logical mux channel. The nodes are adapted to carry out operations utilizing a given logical mux channel associated therewith in order to identify a logical channel that is associated with the given logical mux channel and that has a predetermined ready state. In the preferred embodiment, the operations are invoked by a calling thread that is blocked in the event that no logical channel associated with the given logical mux channel has a predetermined ready state. The calling thread is then reactivated in the event that at least one logical channel associated with the given logical mux channel transitions to the predetermined ready state.

Abstract: A system-on-chip integrated circuit (and multi-chip systems based thereon) that includes a bridge interface that provides transparent bridging of data communicated between integrated circuits.

Abstract: A system-on-chip integrated circuit (and multi-chip systems based thereon) that includes a bridge interface that employs data scrambling and error correction on data communicated between integrated circuits.

Abstract: An integrated circuit having an array of programmable processing elements linked by an on-chip communication network. Each processing element includes a plurality of processing cores, a local memory, and thread scheduling means for scheduling execution of threads on the processing cores of the given processing element. The thread scheduling means assigns threads to the processing cores of the given processing element in a configurable manner. The configuration of the thread scheduling means defines one or more logical symmetric multiprocessors for executing threads on the given processing element. A logical symmetric multiprocessor is realized by a defined set of processing cores assigned to a group of threads executing on the given processing element.

Abstract: Techniques and articles of manufacture are provided comprising computer readable programs that, when executed on the computer, cause the computer to delete a leaf from a Patricia tree having a direct table and a plurality of PSCB's which decode portions of the pattern of a leaf in the tree without shutting down the functioning of the tree. A leaf having a pattern is identified as a leaf to be deleted. Using the pattern, the tree is walked to identify the location of the leaf to be deleted. The leaf to be deleted is identified and deleted, and any relevant PSCB modified, if necessary. The technique also is applicable to deleting a prefix of a prefix.

Abstract: A technique is provided to delete a leaf from a Patricia tree having a direct table and a plurality of PSCB's which decode portions of the pattern of a leaf in the tree without shutting down the functioning of the tree. A leaf having a pattern is identified as a leaf to be deleted. Using the pattern, the tree is walked to identify the location of the leaf to be deleted. The leaf to be deleted is identified and deleted, and any relevant PSCB modified, if necessary. The technique also is applicable to deleting a prefix of a prefix.

Abstract: The present invention relates to a method for storing a plurality of multi-field classification rules in a computer system. Each multi-field classification rule includes a rule specification that itself includes a plurality of fields and a plurality of field definitions corresponding to the fields. The method of the present invention includes providing a virtual rule table, where the table stores a plurality of field definitions, and for each of the plurality of multi-field classification rules, compressing the rule specification by replacing at least one field definition with an associated index into the virtual rule table. The method also includes storing each of the compressed rule specifications and the virtual rule table in a shared segment of memory.

Abstract: A generic method and apparatus for managing semaphores in a multi-threaded processing system has a storage area for each of the threads in the processing system. Each storage area includes a first part for storing at least one indicia for identifying at least one unique semaphore from a plurality of semaphores utilized by the multi-threaded processing system and a second part for storing an indicia for indicating a locked status for the stored semaphore. A thread requiring a semaphore sends a semaphore lock request to the semaphore manager which examines the contents of all of the storage areas to determine the status of the requested semaphore. If the requested semaphore is not locked, it is locked for the requesting thread by inserting the requested semaphore and locked status in the memory location assigned to the requesting thread.

Abstract: The present invention relates to a system for managing a plurality of multi-field classification rules. The system provides a first table that includes a plurality of entries corresponding to a plurality of rules relating to an ingress context and a second table that includes a plurality of entries corresponding to a plurality of rules relating to an egress context. The system also includes a network processor for classifying packets of information, wherein the network processor is programmed to utilize the first table and the second table to identify any rules relating to the ingress context and any one rules relating to the egress context that match a search key.

Abstract: A method and system for transmitting packets in a packet switching network. Packets received by a packet processor may be prioritized based on the urgency to process them. Packets that are urgent to be processed may be referred to as real-time packets. Packets that are not urgent to be processed may be referred to as non-real-time packets. Real-time packets have a higher priority to be processed than non-real-time packets. A real-time packet may either be discarded or transmitted into a real-time queue based upon its value priority, the minimum and maximum rates for that value priority and the current real-time queue congestion conditions. A non-real-time packet may either be discarded or transmitted into a non-real-time queue based upon its value priority, the minimum and maximum rates for that value priority and the current real-time and non-real-time queue congestion conditions.

Abstract: A procedure is used to provide data structures that handle large numbers of active data entries and a high rate of additions and deletions of active entries. The procedure utilizes one or more of the following modifications. Timers are removed from individual session table entries and are linked via pointers. Bilateral links are established between the session table and the timer structure. Aging/timer checks are applied to the timer control block (TCB). A chain of TCBs, optionally including an excess of blocks, may be used along with packing of multiple TCBs into a single memory location. This excess of blocks permits a terminated session to continue to occupy a TCB until the timer process progresses to that block location in the chain of blocks.

Abstract: The present invention relates to a method for managing a plurality of multi-field classification rules. The method includes providing a first table that includes a plurality of entries corresponding to a plurality of rules relating to an ingress context and providing a second table that includes a plurality of entries corresponding to a plurality of rules relating to an egress context. The method also includes utilizing the first table and the second table to identify any rules relating to the ingress context and any rules relating to the egress context that match a search key.