Patents by Inventor Marco Mastrapasqua
Marco Mastrapasqua has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20140292152Abstract: A resonator device in which a piezoelectric material is disposed between two electrodes. At least one of the electrodes is formed of a nickel-titanium alloy having equal portions nickel and titanium.Type: ApplicationFiled: March 31, 2014Publication date: October 2, 2014Applicant: Cymatics Laboratories Corp.Inventors: Peter Ledel Gammel, Marco Mastrapasqua, Hugo Safar, Rajarishi Sinha
-
Publication number: 20140022009Abstract: The present invention is directed to monolithic integrated circuits incorporating an oscillator element that are particularly suited for use in timing applications. The oscillator element includes a resonator element having a piezoelectric material disposed between a pair of electrodes. The oscillator element also includes an acoustic confinement structure that may be disposed on either side of the resonator element. The acoustic confinement element includes alternating sets of low and high acoustic impedance materials. A temperature compensation layer may be disposed between the piezoelectric material and at least one of the electrodes. The oscillator element is monolithically integrated with an integrated circuit element through an interconnection. The oscillator element and the integrated circuit element may be fabricated sequentially or concurrently.Type: ApplicationFiled: September 27, 2013Publication date: January 23, 2014Applicant: CYMATICS LABORATORIES CORP.Inventors: Rajarishi Sinha, Peter Ledel Gammel, Marco Mastrapasqua, Hugo Safar
-
Patent number: 8564174Abstract: The present invention is directed to monolithic integrated circuits incorporating an oscillator element that is particularly suited for use in timing applications. The oscillator element includes a resonator element having a piezoelectric material disposed between a pair of electrodes. The oscillator element also includes an acoustic confinement structure that may be disposed on either side of the resonator element. The acoustic confinement element includes alternating sets of low and high acoustic impedance materials. A temperature compensation layer may be disposed between the piezoelectric material and at least one of the electrodes. The oscillator element is monolithically integrated with an integrated circuit element through an interconnection. The oscillator element and the integrated circuit element may be fabricated sequentially or concurrently.Type: GrantFiled: December 29, 2011Date of Patent: October 22, 2013Assignee: Cymatics Laboratories Corp.Inventors: Rajarishi Sinha, Peter Ledel Gammel, Marco Mastrapasqua, Hugo Safar
-
Publication number: 20120098611Abstract: The present invention is directed to monolithic integrated circuits incorporating an oscillator element that is particularly suited for use in timing applications. The oscillator element includes a resonator element having a piezoelectric material disposed between a pair of electrodes. The oscillator element also includes an acoustic confinement structure that may be disposed on either side of the resonator element. The acoustic confinement element includes alternating sets of low and high acoustic impedance materials. A temperature compensation layer may be disposed between the piezoelectric material and at least one of the electrodes. The oscillator element is monolithically integrated with an integrated circuit element through an interconnection. The oscillator element and the integrated circuit element may be fabricated sequentially or concurrently.Type: ApplicationFiled: December 29, 2011Publication date: April 26, 2012Applicant: CYMATICS LABORATORIES CORP.Inventors: Rajarishi Sinha, Peter Ledel Gammel, Marco Mastrapasqua, Hugo Safar
-
Patent number: 8089195Abstract: The present invention is directed to monolithic integrated circuits incorporating an oscillator element that is particularly suited for use in timing applications. The oscillator element includes a resonator element having a piezoelectric material disposed between a pair of electrodes. The oscillator element also includes an acoustic confinement structure that may be disposed on either side of the resonator element. The acoustic confinement element includes alternating sets of low and high acoustic impedance materials. A temperature compensation layer may be disposed between the piezoelectric material and at least one of the electrodes. The oscillator element is monolithically integrated with an integrated circuit element through an interconnection. The oscillator element and the integrated circuit element may be fabricated sequentially or concurrently.Type: GrantFiled: December 17, 2007Date of Patent: January 3, 2012Assignee: Resonance Semiconductor CorporationInventors: Rajarishi Sinha, Peter Ledel Gammel, Marco Mastrapasqua, Hugo Safar
-
Publication number: 20090152983Abstract: The present invention is directed to monolithic integrated circuits incorporating an oscillator element that is particularly suited for use in timing applications. The oscillator element includes a resonator element having a piezoelectric material disposed between a pair of electrodes. The oscillator element also includes an acoustic confinement structure that may be disposed on either side of the resonator element. The acoustic confinement element includes alternating sets of low and high acoustic impedance materials. A temperature compensation layer may be disposed between the piezoelectric material and at least one of the electrodes. The oscillator element is monolithically integrated with an integrated circuit element through an interconnection. The oscillator element and the integrated circuit element may be fabricated sequentially or concurrently.Type: ApplicationFiled: December 17, 2007Publication date: June 18, 2009Applicant: Renaissance WirelessInventors: Rajarishi Sinha, Peter Ledel Gammel, Marco Mastrapasqua, Hugo Safar
-
Publication number: 20080003703Abstract: In a metal-oxide semiconductor device including first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, a drift region formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions, an insulating layer formed on at least a portion of the upper surface of the semiconductor layer, and a gate formed on the insulating layer and at least partially between the first and second source/drain regions, a method for controlling an amount of hot carrier injection degradation in the device includes the steps of: forming a shielding structure on the insulating layer above at least a portion of the drift region and substantially between the gate and the second source/drain region; and adjusting an amount of coverage of the shielding structure over an upper surface of the drift region so as to minimizType: ApplicationFiled: September 11, 2007Publication date: January 3, 2008Inventors: Peter Gammel, Isik Kizilyalli, Marco Mastrapasqua, Muhammed Shibib, Zhijian Xie, Shuming Xu
-
Publication number: 20050156234Abstract: An MOS device is formed including a semiconductor layer of a first conductivity type, and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A drift region is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. An insulating layer is formed on at least a portion of the upper surface of the semiconductor layer and above at least a portion of the drift region. A gate is formed on the insulating layer and at least partially between the first and second source/drain regions. The MOS device further includes a shielding structure formed on the insulating layer above at least a portion of the drift region.Type: ApplicationFiled: October 29, 2004Publication date: July 21, 2005Inventors: Peter Gammel, Isik Kizilyalli, Marco Mastrapasqua, Muhammed Shibib, Zhijian Xie, Shuming Xu
-
Patent number: 6509242Abstract: A heterojunction bipolar transistor includes an emitter or collector region of doped silicon, a base region including silicon-germanium, and a spacer. The emitter or collector region form a heterojunction with the base region. The spacer is positioned to electrically insulate the emitter or collector region from an external region. The spacer includes a silicon dioxide layer physically interposed between the emitter or collector region and the remainder of the spacer.Type: GrantFiled: January 12, 2001Date of Patent: January 21, 2003Assignee: Agere Systems Inc.Inventors: Michel Ranjit Frei, Clifford Alan King, Yi Ma, Marco Mastrapasqua, Kwok K Ng
-
Publication number: 20020093031Abstract: A heterojunction bipolar transistor includes an emitter or collector region of doped silicon, a base region including silicon-germanium, and a spacer. The emitter or collector region form a heterojunction with the base region. The spacer is positioned to electrically insulate the emitter or collector region from an external region. The spacer includes a silicon dioxide layer physically interposed between the emitter or collector region and the remainder of the spacer.Type: ApplicationFiled: January 12, 2001Publication date: July 18, 2002Inventors: Michel Ranjit Frei, Clifford Alan King, Yi Ma, Marco Mastrapasqua, Kwok K Ng
-
Patent number: 6303940Abstract: The present invention relates to a heterojunction structure based upon the oxide/high-k dielectric barrier. In exemplary embodiment, a silicon layer has a silicon dioxide layer thereon, and a high-k dielectric material disposed on the oxide layer. Thereafter, a metal layer, serving as the gate metal for the device is disposed on the high-k dielectric. The silicon dioxide layer has a relatively high barrier height, but has a relatively small thickness, and relative to the high-k dielectric, the barrier height differential fosters real space transfer. In this structure, the high barrier height of the silicon dioxide layer results in higher mobility and thereby greater substrate current. By virtue of the relative thick layer of high-k dielectric, leakage current is significantly reduced.Type: GrantFiled: June 25, 1999Date of Patent: October 16, 2001Assignee: Agere Systems Guardian Corp.Inventors: Isik C. Kizilyalli, Marco Mastrapasqua
-
Patent number: 6144073Abstract: A monolithically-integrated SRAM cell is described for reducing the cell size, i.e., at least two of a plurality of transistors comprising the SRAM cell are monolithically integrated to define a first transistor and a second transistor, wherein the drain of the first transistor functions as the gate of the second transistor and the drain of the second transistor functions as the gate of the first transistor. This integration eliminates the need for gate-to-drain connections of previous devices.Type: GrantFiled: May 13, 1999Date of Patent: November 7, 2000Assignee: Lucent Technologies Inc.Inventors: Gerhard Hobler, Marco Mastrapasqua, Mark Richard Pinto, Enrico Sangiori
-
Patent number: 6011722Abstract: A method for programming and/or erasing an array of stacked gate memory devices such as EPROM and EEPROM devices in a NOR array is disclosed. In the method, either a program verify or an erase verify is performed intermittently with the programming of a device or the erasure of the array. During the program-verify, one of either a negative V.sub.CS is applied to the deselected devices in the array, a negative V.sub.BS is applied to both the selected and deselected devices in the array, or both conditions are applied. Performing the program verify or erase verify in this manner is efficient and accurate. During the programming step, it is also advantageous if one of either a negative V.sub.CS is applied to the deselected devices in the array, a negative V.sub.BS is applied to the selected devices in the array, or both. With the application of a negative V.sub.Type: GrantFiled: October 13, 1998Date of Patent: January 4, 2000Assignee: Lucent Technologies Inc.Inventors: Jeffrey Devin Bude, Marco Mastrapasqua
-
Patent number: 6002610Abstract: An integrated circuit includes at least one non-volatile memory element having first and second non-volatile transistors connected in series between first and second data lines. A junction between the first and second non-volatile transistors forms an output node. The non-volatile memory element further includes an access transistor connected between a reference voltage line and the junction between the first and second non-volatile transistors. In a programmable logic application, for example a field programmable gate array, the non-volatile memory element controls the state of a switching element, which selectively connects logic elements in the programmable logic application. Based on the voltages applied to the non-volatile memory element, the non-volatile memory element is selectively erased, programmed, operated, monitored and powered-up.Type: GrantFiled: April 30, 1998Date of Patent: December 14, 1999Assignee: Lucent Technologies Inc.Inventors: Hong-Ih Louis Cong, Jeffrey Devin Bude, Marco Mastrapasqua