Patents by Inventor Marco Messina
Marco Messina has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9378157Abstract: Various embodiments comprise apparatuses and methods to allow access to a memory device by an external device. A method includes receiving, at the memory device, a request from the external device to access a storage area of the memory device and performing an unlock procedure of the storage area. The unlock procedure includes sending a first code from the memory device to the external device, and receiving a second code at the memory device from the external device. The second code is to be generated by a first encryption process performed on the first code to obtain the second code. The storage area is temporarily unlocked to allow the external device to access the storage area based on a determination that the received second code has a predetermined relationship to the first code. Additional apparatuses and methods are described.Type: GrantFiled: July 7, 2014Date of Patent: June 28, 2016Assignee: Micron Technology, Inc.Inventors: Marco Messina, Antonino Capri', Salvatore Giove, Antonino La Spina, Vijay Malhi
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Publication number: 20140325176Abstract: Various embodiments comprise apparatuses and methods to allow access to a memory device by an external device. A method includes receiving, at the memory device, a request from the external device to access a storage area of the memory device and performing an unlock procedure of the storage area. The unlock procedure includes sending a first code from the memory device to the external device, and receiving a second code at the memory device from the external device. The second code is to be generated by a first encryption process performed on the first code to obtain the second code. The storage area is temporarily unlocked to allow the external device to access the storage area based on a determination that the received second code has a predetermined relationship to the first code. Additional apparatuses and methods are described.Type: ApplicationFiled: July 7, 2014Publication date: October 30, 2014Inventors: Marco Messina, Antonino Capri', Salvatore Giove, Antonino La Spina, Vijay Malhi
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Patent number: 8844023Abstract: A semiconductor memory may be provided with a built-in test mode that is accessible through a password protection scheme. This enables access to a built-in test mode after manufacturing, if desired. At the same time, the password protection prevents use of the built-in test mode to bypass security features of the memory.Type: GrantFiled: December 2, 2008Date of Patent: September 23, 2014Assignee: Micron Technology, Inc.Inventors: Antonino La Malfa, Marco Messina
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Patent number: 8776174Abstract: Various embodiments comprise apparatuses and methods to allow access to a memory device by an external device. A method includes receiving, at the memory device, a request from the external device to access a storage area of the memory device and performing an unlock procedure of the storage area. The unlock procedure includes sending a first code from the memory device to the external device, and receiving a second code at the memory device from the external device. The second code is to be generated by a first encryption process performed on the first code to obtain the second code. The storage area is temporarily unlocked to allow the external device to access the storage area based on a determination that the received second code has a predetermined relationship to the first code. Additional apparatuses and methods are described.Type: GrantFiled: September 13, 2012Date of Patent: July 8, 2014Assignee: Micron Technology, Inc.Inventors: Marco Messina, Antonino Capriā², Salvatore Giove, Antonino La Spina, Vijay Malhi
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Publication number: 20130014215Abstract: Various embodiments comprise apparatuses and methods to allow access to a memory device by an external device. A method includes receiving, at the memory device, a request from the external device to access a storage area of the memory device and performing an unlock procedure of the storage area. The unlock procedure includes sending a first code from the memory device to the external device, and receiving a second code at the memory device from the external device. The second code is to be generated by a first encryption process performed on the first code to obtain the second code. The storage area is temporarily unlocked to allow the external device to access the storage area based on a determination that the received second code has a predetermined relationship to the first code. Additional apparatuses and methods are described.Type: ApplicationFiled: September 13, 2012Publication date: January 10, 2013Inventors: Marco MESSINA, Antonino CAPRI', Salvatore GIOVE, Antonino LA SPINA, Vijay MALHI
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Patent number: 8276185Abstract: A memory device includes: at least one storage area for storing data; a protection control structure adapted to selectively allow an external device access to the at least one storage area of the memory, the storage area being not freely accessible by the external device if protected; a control logic adapted to identify an access request by the external device to the at least one storage area and cooperating with the protection control structure for managing an unlock procedure for selectively granting the external device at least temporary access rights to the storage area if protected; means for providing a first code to the external device in said unlock procedure; means for receiving a second code from the external device in response to said first code; means for verifying validity of the received second code. The means for verifying validity are adapted to ascertain a correspondence of the second code with the first code based on a predetermined relationship.Type: GrantFiled: January 19, 2006Date of Patent: September 25, 2012Assignee: Micron Technology, Inc.Inventors: Marco Messina, Antonino Capri', Salvatore Giove, Antonino La Spina, Vijay Malhi
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Publication number: 20100138915Abstract: In accordance with some embodiments, a semiconductor memory may be provided with a built-in test mode that is accessible through a password protection scheme. This enables access to a built-in test mode after manufacturing, if desired. At the same time, the password protection prevents use of the built-in test mode to bypass security features of the memory.Type: ApplicationFiled: December 2, 2008Publication date: June 3, 2010Inventors: Antonino La Malfa, Marco Messina
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Patent number: 7535774Abstract: A circuit is for generating an internal enabling signal for the output buffer of a memory as a function of external commands for enabling the memory and for outputting data. The circuit may be input with the external command for enabling the memory and with internally generated flags signaling when the memory is being read and when a read operation of data from the memory ends. The circuit may generate a first intermediate signal having a null logic value when the memory is enabled and the read operation of data from the memory ends. The circuit may further generate the internal enabling signal as a logic NOR between the first intermediate signal and a logic OR between the external command enabling the memory and the external command for outputting data.Type: GrantFiled: January 20, 2006Date of Patent: May 19, 2009Inventors: Antonino La Malfa, Marco Messina
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Publication number: 20080189557Abstract: A memory device including at least one storage area for storing data and a protection control structure adapted to selectively allow an external device access to the at least one storage area of the memory, the storage area being not freely accessible by the external device if protected. The memory device further includes a control logic adapted to identify an access request by the external device to the at least one storage area and cooperating with the protection control structure for managing an unlock procedure for selectively granting the external device at least temporary access rights to the storage area if protected.Type: ApplicationFiled: January 19, 2006Publication date: August 7, 2008Inventors: Francesco Pipitone, Francesco Tomaiuolo, Marco Messina, Alessandro Raimondo, Vijay Malhi, Salvatore Giove
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Patent number: 7336117Abstract: A dual power supply digital device includes a down converter for converting an externally applied supply voltage to a regulated first supply voltage for powering a core part of the logic circuitry of the digital device. A second supply voltage source provides a second supply voltage for powering input buffers of the I/O pads of the digital device. A voltage translator latch stage may be powered at the regulated down converted first supply voltage for replicating a stored inverted replica of a logic value present on a respective I/O pad of the digital device onto an input node of a respective second input logic buffer powered at the regulated core supply voltage. The device may further include a transistor having a turn-on threshold coupling the input node of the second buffer to the regulated down converted core supply voltage, with the transistor having a control gate connected to the second power supply source.Type: GrantFiled: July 14, 2006Date of Patent: February 26, 2008Assignee: STMicroelectronics S.r.l.Inventors: Antonino La Malfa, Marco Messina
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Publication number: 20080012621Abstract: A dual power supply digital device includes a down converter for converting an externally applied supply voltage to a regulated first supply voltage for powering a core part of the logic circuitry of the digital device. A second supply voltage source provides a second supply voltage for powering input buffers of the I/O pads of the digital device. A voltage translator latch stage may be powered at the regulated down converted first supply voltage for replicating a stored inverted replica of a logic value present on a respective I/O pad of the digital device onto an input node of a respective second input logic buffer powered at the regulated core supply voltage. The device may further include a transistor having a turn-on threshold coupling the input node of the second buffer to the regulated down converted core supply voltage, with the transistor having a control gate connected to the second power supply source.Type: ApplicationFiled: July 14, 2006Publication date: January 17, 2008Applicant: STMicroelectronics S.r.l.Inventors: Antonino LA MALFA, Marco MESSINA
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Publication number: 20070192828Abstract: A memory device includes: at least one storage area for storing data; a protection control structure adapted to selectively allow an external device access to the at least one storage area of the memory, the storage area being not freely accessible by the external device if protected; a control logic adapted to identify an access request by the external device to the at least one storage area and cooperating with the protection control structure for managing an unlock procedure for selectively granting the external device at least temporary access rights to the storage area if protected; means for providing a first code to the external device in said unlock procedure; means for receiving a second code from the external device in response to said first code; means for verifying validity of the received second code. The means for verifying validity are adapted to ascertain a correspondence of the second code with the first code based on a predetermined relationship.Type: ApplicationFiled: January 19, 2006Publication date: August 16, 2007Inventors: Marco Messina, Antonino Capri, Salvatore Giove, Antonino La Spina, Vijay Malhi
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Patent number: 7139397Abstract: A hybrid architecture for realizing a random numbers generator comprising a digital circuitry portion able to provide for a random bytes sequence as well as an analog circuitry portion able to provide a seed of the true random type is described.Type: GrantFiled: July 18, 2002Date of Patent: November 21, 2006Assignee: STMicroelectronics S.r.l.Inventors: Marco Messina, Salvatore Polizzi, Giulio Mangione
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Patent number: 7120062Abstract: Described herein is a method for soft-programming an electrically erasable nonvolatile memory device, wherein soft-programming is carried out with a soft-programming multiplicity equal to twice that used for writing data in the memory device until the current absorbed during soft-programming is smaller than or equal to the maximum current which is available for writing operations and which can be generated within the memory device, and with a soft-programming multiplicity equal to the one used for writing data in the memory device in the case where the current absorbed during soft-programming with double multiplicity is greater than the maximum current which is available for writing operations and which can be generated within the memory device.Type: GrantFiled: February 17, 2004Date of Patent: October 10, 2006Assignee: STMicroelectroniics S.r.l.Inventors: Antonino La Malfa, Marco Messina
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Patent number: 7099906Abstract: A random-bit sequence generator includes a biasing circuit, a source of a noisy voltage signal biased by the biasing circuit, an amplification stage generating an amplified signal representative of the sole non-zero-frequency (AC) component of the noisy voltage signal and an output stage electrically in cascade to the amplification stage that generates a random bit sequence in function of the amplified signal. The generator also filters the undesired low-frequency disturbance components because the amplification stage comprises an input low-pass filter that feeds the zero- (DC) component of the noisy voltage signal to one of the inputs of a differential amplifier, to another input of which is fed the non-filtered noisy voltage signal.Type: GrantFiled: October 11, 2002Date of Patent: August 29, 2006Assignee: STMicroelectronics, S.r.l.Inventors: Marco Messina, Antonino La Malfa
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Publication number: 20060181311Abstract: A circuit is for generating an internal enabling signal for the output buffer of a memory as a function of external commands for enabling the memory and for outputting data. The circuit may be input with the external command for enabling the memory and with internally generated flags signaling when the memory is being read and when a read operation of data from the memory ends. The circuit may generate a first intermediate signal having a null logic value when the memory is enabled and the read operation of data from the memory ends. The circuit may further generate the internal enabling signal as a logic NOR between the first intermediate signal and a logic OR between the external command enabling the memory and the external command for outputting data.Type: ApplicationFiled: January 20, 2006Publication date: August 17, 2006Applicant: STMicroelectronics S.r.l.Inventors: Antonino La Malfa, Marco Messina
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Publication number: 20040223361Abstract: Described herein is a method for soft-programming an electrically erasable nonvolatile memory device, wherein soft-programming is carried out with a soft-programming multiplicity equal to twice that used for writing data in the memory device until the current absorbed during soft-programming is smaller than or equal to the maximum current which is available for writing operations and which can be generated within the memory device, and with a soft-programming multiplicity equal to the one used for writing data in the memory device in the case where the current absorbed during soft-programming with double multiplicity is greater than the maximum current which is available for writing operations and which can be generated within the memory device.Type: ApplicationFiled: February 17, 2004Publication date: November 11, 2004Applicant: STMicroelectronics S.r.I.Inventors: Antonino La Malfa, Marco Messina
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Patent number: 6785174Abstract: An electronic memory device monolithically integrated in semiconductor has a low pin count (LPC) serial interface. The memory device includes a memory cell array and associated row and column decode circuits. The memory device also includes a bank of T-latch registers to be addressed and accessed in a test mode for serially loading specific test data therein. The serially loading includes activating a test mode of operation by an address storage block for generating a corresponding signal, enabling the bank of T-latch registers in the device to serially receive a predetermined data set, and loading test data into the T-latch registers by using a LPC serial communication protocol.Type: GrantFiled: May 28, 2003Date of Patent: August 31, 2004Assignee: STMicroelectronics S.r.l.Inventors: Marco Messina, Maurizio Perroni, Salvatore Polizzi
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Publication number: 20040071028Abstract: An electronic memory device monolithically integrated in semiconductor has a low pin count (LPC) serial interface. The memory device includes a memory cell array and associated row and column decode circuits. The memory device also includes a bank of T-latch registers to be addressed and accessed in a test mode for serially loading specific test data therein. The serially loading includes activating a test mode of operation by an address storage block for generating a corresponding signal, enabling the bank of T-latch registers in the device to serially receive a predetermined data set, and loading test data into the T-latch registers by using a LPC serial communication protocol.Type: ApplicationFiled: May 28, 2003Publication date: April 15, 2004Applicant: STMicroelectronics S.r.l.Inventors: Marco Messina, Maurizio Perroni, Salvatore Polizzi
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Publication number: 20030093455Abstract: A random-bit sequence generator comprises a biasing circuit, a source of a noisy voltage signal biased by the biasing circuit, an amplification stage generating an amplified signal representative of the sole AC component of the noisy voltage signal and an output stage electrically in cascade to the amplification stage that generates a random bit sequence in function of the amplified signal. The generator also filters the undesired low-frequency disturbance components because the amplification stage comprises an input low-pass filter that feeds the DC component of the noisy voltage signal to one of the inputs of a differential amplifier, to another input of which is fed the non filtered noisy voltage signal.Type: ApplicationFiled: October 11, 2002Publication date: May 15, 2003Inventors: Marco Messina, Antonino La Malfa