Abstract: A circuit comprises a section generating a pulse signal for asynchronously enabling the read phases; a section generating precharge and detecting signals of adjustable duration, for controlling data reading from the memory and data supply to the output buffers; a section generating a noise suppressing signal for freezing the data in the output buffers during loading into the output circuits, and the duration of which is exactly equal to the propagation time of the data to the output circuits of the memory, as determined by propagating a data simulating signal in an output simulation circuit; a section generating a loading signal, the duration of which may be equal to that of the noise suppressing signal or extended by an extension circuit in the event the array presents slower elements which may thus be read; and a section generating a circuit reset signal.

Abstract: A voltage regulator for programming non-volatile memory cells, which comprises an amplifier stage being powered between a first and a second voltage reference and having a first input terminal connected to a resistive divider of the first reference voltage and an output terminal fed back to said input through a current mirror, and a source-follower transistor controlled by the output and connected to the cells through a programming line. Also provided is a MOS transistor which connects to ground the programming line and a corresponding resistive path connected between the current mirror and the second voltage reference.

Abstract: A load timing circuit including an output simulation circuit similar to the output circuits of the memory, so as to present the same propagation delay; a simulating signal source for generating a data simulating signal; a synchronizing network for detecting a predetermined switching edge of the data simulating signal and enabling supply of the signal to the output simulation circuit and data supply to the output circuits of the memory; a combinatorial network for detecting propagation of the data simulating signal to the output of the output simulation circuit and disabling the data simulating signal; and a reset element for resetting the timing circuit.

Abstract: There is described a semiconductor memory including a matrix of rows and columns of memory cells, wherein the columns are grouped together in sectors, each sector representing the portion of the matrix itself related to a data input/output line. Each sector is in turn divided into packets of columns, and there are redundancy columns suitable for replacing a matrix column containing defective memory cells. Each of the redundancy columns is included in a respective packet. The memory also includes control circuits to execute the abovementioned replacement.

Abstract: The discriminating sensitivity of a sense amplifier and the speed of the circuit are increased by exploiting the difference of potential which develops across the output nodes of the two control circuits, employed for enabling/disabling current paths of the input network of the differential amplifier, as a virtual additional signal for the sensing differential amplifier, by employing said output potentials of the two control circuits as virtual reference potentials for the pair of input transistors of the differential amplifier during a discriminating phase of the reading cycle. Two pass-transistors driven by a control signal provide to force to ground potential the output nodes of said control circuits, thus reestablishing a correct ground reference potential of the amplifier, during the final phase of amplification and storage of the extracted datum in an output latch, as well as during the successive standby period. Alternative embodiments also include various anti-overshoot circuits.

Abstract: Spurious memory readings which may be caused by noise induced by transitions in the output buffers of a fast parallel memory device are prevented by permitting output latches to change state in function of newly extracted data signals by means of an enabling pulse having a preestablished duration and which is generated only after a change of memory address signals has occurred and the new configuration of memory address signals has lasted for a time which is not shorter than the time of propagation of signals through the memory chain. The enabling pulse is generated by employing a detector of transitions occurring in the input circuitry of the memory, a dummy memory chain, a one-shot pulse generator and a resetting pulse generator. The anti-noise network may be exploited also for implementing an auto-stand-by condition at the end of each read cycle, which reduces power consumption and increases speed by simplifying the sensing process.

Abstract: A power-on reset circuit, which may be utilized with CMOS integrated circuits, includes first and second series-connected inverters, wherein the output of the second inverter provides a reset signal. A series of switches and a biasing line having two series-connected diodes are integrally arranged with the inverters. Capacitive coupling to ground and the supply voltage is employed to prevent any static current path between supply voltage rails. The circuit provides a short duration reset signal which follows the supply voltage and is insensitive both to rebound signals on the supply voltage rails and to internal and external noise.

Abstract: The sense circuit recognizes the virgin or programmed status of cells in storage devices (e.g. non-volatile memories of the type with unbalanced loads), and includes a sense amplifier (SA) having a first input (Y) connected to a number of selectable virgin reference cells (T.sub.vr1, T.sub.vr2) and a second input (X) connected to a number of selectable matrix cells (T.sub.vm, T.sub.pm). According to the invention, the current path of a compensatory programmed cell (NP) is connected between a reference voltage and the first input (Y) of the sense amplifier (SA), with the gate of the compensatory programmed cell being connected to a voltage source (Vs) which selects the compensatory programmed cell at least while the sense amplifier reads a selected matrix cell.

Abstract: A non-volatile memory in which, during read operations, the sense amplifier's first input is connected not only to a selected non-programmed reference cell, but also to a current of a value one half the current that flows in a programmed cell; and the sense amplifier's second input is connected not only to a selected matrix cell to be read, but also to a current of a value one half the current that flows in a non-programmed cell.

Abstract: A sense circuit for reading EPROM and ROM type memory cells employs a circuit for generating an offsetting current which is exempt of error during transients and which thus permits to achieve a reduced access time. On the other hand, the sense circuit maintains the intrinsic advantages of a current-offset sensing architecture which is represented by a substantially unlimited operating voltage range toward the maximum value VCC.sub.max. The current generating circuit is driven by means of a supplementary row of cells which is decoded at every reading and which replicates, during transients, the behaviour of the row selected for the reading.

Abstract: A voltage-boosted phase oscillator for driving a voltage multiplier comprises two intermeshed ring oscillators, each composed by an odd number of inverters connected in cascade through a closed loop and generating a normal phase and a voltage-boosted phase derived from the normal phase through a bootstrap circuit. The frequency of oscillation of both intermeshed ring oscillators is established by means of two similar RC networks common to both loops. The synchronization of the respective oscillations of the two rings is ensured by means of a plurality of SR flip-flops connected in cascade, formed by two NAND gates which, singularly, constitute as many inverters of the two rings. The oscillation and the arresting of the oscillation are controlled by means of a logic signal fed to a common input of a first pair of NAND gates which constitute respectively a first inverter of the relative ring oscillator and to a second input of which the phase produced by the relative ring oscillator is fed.

Abstract: A reference cell for reading EEPROM memory devices, capable of discharging any charges present in its own floating gate without varying the geometry of the cell with respect to that of the associated memory cells and without requiring specific manufacturing steps. For this purpose, a switch element, for example a diode, is provided between the floating gate and the substrate of the device and discharges any charges present in the floating gate toward the substrate during the cell idle state in the absence of read signals.

Abstract: A CMOS logic circuit for converting a low voltage logic signal with a range O-VCC into a high voltage logic signal with a range O-VPP, which may be entirely made with enhancement-type transistors, comprises an additional p-channel, decoupling transistor functionally connected in series with the p-channel transistor of the CMOS circuit which is connected to the high voltage node VPP and the additional decoupling transistor is driven by a bias voltage tied to the VPP voltage and lower than the latter by a certain preset value. The so-called gated breakdown of p-channel transistors is effectively prevented and furthermore these circuits, destined to operate under a high supply voltage, may be fabricated through a normal CMOS fabrication process not requiring particular fabrication techniques for the p-channel transistors subject to gated breakdown conditions or the formation of depletion-type transistors and without the use of special circuits which require oscillator generated driving signals.

Abstract: The regulation of the output voltage of a voltage multiplier driven by a ring oscillator, an inverter of which is substituted by a NOR gate for providing a terminal through which stopping the oscillation, is effected by controlling the oscillation frequency in function of the current delivered by the voltage multiplier by means of a transistor T1 working as a current generator connected in series with a regulating chain of series-connected diodes by biasing the gate of the transistor with a constant voltage Vref, thus imposing a reference current Iref through the transistor. The voltage signal across the transistor is fed to the input of a first inverter with a preset triggering threshold and the output signal of the inverter is fed through an amplifying and phase-regenerating stage to said terminal for stopping the oscillation of said NOR gate of the ring oscillator.

Abstract: A wholly integrated, multistage, CMOS voltage multiplier utilizes as a diode structure for transferring electric charge from an input node to an output node of each stage an enhancement type MOS transistor, the gate of which is coupled to the same switching phase to which the output capacitor of the stage is connected by means of a coupling capacitor. During a semicycle of charge transfer through said MOS transistor, the coupling capacitor charges through a second MOS transistor of the same type and having the same threshold of said charge transfer MOS transistor, connected in a diode configuration between the output node of the stage and the gate of the charge transfer MOS transistor, in order to cut-off the latter when reaching a voltage lower than the voltage reached by the output node by a value equal to the threshold value of said second transistor.

Abstract: The regulation of the output voltage of a voltage multiplier driven by a ring oscillator, an inverter of which is substituted by a NOR gate for providing a terminal through which stopping the oscillation, is effected by controlling the oscillation frequency in function of the current delivered by the voltage multiplier by means of a transistor T1 working as a current generator connected in series with a regulating chain of series-connected diodes by biasing the gate of the transistor with a constant voltage Vref, thus imposing a reference current Iref through the transistor. The voltage signal across the transistor is fed to the input of a first inverter with a preset triggering threshold and the output signal of the inverter is fed through an amplifying and phase-regenerating stage to said terminal for stopping the oscillation of said NOR gate of the ring oscillator.