Abstract: Methods, systems, and devices for commanded device states for a memory system are described. For example, a memory system may be configured with different device states that are each associated with a respective allocation of resources (e.g., feature sets) for operations of the memory system. Resource allocations corresponding to the different device states may be associated with different combinations of memory management configurations, error control configurations, trim parameters, degrees of parallelism, or endurance configurations, among other parameters of the memory system, which may support different tradeoffs between performance characteristics of the memory system. A host system may be configured to evaluate various parameters of operating the host system, and to transmit commands for a memory system to enter a desired device state of the memory system.

Abstract: Methods, systems, and devices for techniques for detection of shutdown patterns are described. A memory device may receive a set of commands from a host device. The memory device may determine whether the set of commands are associated with a shutdown procedure based on a pattern of the received set of commands. The memory device may initiate one or more operations associated with the shutdown procedure based on identifying that the set of commands are associated with the shutdown procedure. The memory device may receive a shutdown command for the shutdown procedure after initiating the one or more operations associated with the shutdown procedure. The memory device may determine that the set of commands are associated with the shutdown procedure based on a quantity of the set of commands, one or more types of the set of commands, other thresholds associated with the pattern, or a combination thereof.

Abstract: Methods, systems, and devices for hardware reset management for universal flash storage (UFS) are described. A UFS device may initiate a boot-up procedure that includes multiple phases. The UFS device may perform a first reset operation to reset one or more circuits based on receiving a first reset command during a first phase. The UFS device perform a second phase and may initiate a portion of a second reset operation to reset the one or more circuits during the second phase based on a likelihood that a second reset command is to be received. The UFS device may receive the second reset command during the second phase after initiating the portion of the second reset operation. The UFS device may initiate a second portion of the second reset operation based on receiving the second reset command and initiating the portion of the second reset operation.

Abstract: Methods, systems, and devices are described to indicate, in an entry of logical to physical (L2P) mapping information stored at a host system, whether data associated with the entry is sequential to other data associated with a next entry or a previous entry. Each entry may have a third field, which may indicate whether the data is sequential. Based on the third field, the host system may determine whether data to be read from a memory system is sequential. The host system may transmit one read command to the memory system if the data is sequential, where the read command may include at least a portion of an L2P entry associated with the data. Similarly, based on the third field, the memory system may determine whether the data to be read is sequential, and may read additional, sequential data if the memory system determines that the data is sequential.

Abstract: Methods, systems, and devices for techniques for detection of shutdown patterns are described. A memory device may receive a set of commands from a host device. The memory device may determine whether the set of commands are associated with a shutdown procedure based on a pattern of the received set of commands. The memory device may initiate one or more operations associated with the shutdown procedure based on identifying that the set of commands are associated with the shutdown procedure. The memory device may receive a shutdown command for the shutdown procedure after initiating the one or more operations associated with the shutdown procedure. The memory device may determine that the set of commands are associated with the shutdown procedure based on a quantity of the set of commands, one or more types of the set of commands, other thresholds associated with the pattern, or a combination thereof.

Abstract: Methods, systems, and devices for app launch detection from read chunk analysis are described. Read commands may be received for accessing data stored in a memory system. The read commands may be used to determine a distribution of sizes for associated read data over an interval of time based, at least in part, on receiving the read commands. The memory system may detect the launch of an application based in part on the distribution of the sizes of the read data over the interval of time. Upon detecting the launch of the application, a procedure may be performed to reduce a duration associated with launching the application.

Abstract: Methods, systems, and devices for latency reduction of boot procedures for memory systems are described. A memory system may receive a first command to perform a first reset of one or more components as part of a first phase of a boot procedure of a host system. The memory system may initiate an initialization process of a second phase of the boot procedure upon determining whether the value of a flag has been set from a first value to a second value. Upon completing the initialization process, the flag may be set to the first value. Parameters corresponding to the characteristics of the memory system may be communicated to the host system based on receiving a second command. The memory system may perform a configuration operation of a logical-to-physical mapping concurrently with communicating the parameters with the host system.

Abstract: Methods, systems, and devices for hardware reset management for universal flash storage (UFS) are described. A UFS device may initiate a boot-up procedure that includes multiple phases. The UFS device may perform a first reset operation to reset one or more circuits based on receiving a first reset command during a first phase. The UFS device perform a second phase and may initiate a portion of a second reset operation to reset the one or more circuits during the second phase based on a likelihood that a second reset command is to be received. The UFS device may receive the second reset command during the second phase after initiating the portion of the second reset operation. The UFS device may initiate a second portion of the second reset operation based on receiving the second reset command and initiating the portion of the second reset operation.

Abstract: Methods, systems, and devices are described to indicate, in an entry of logical to physical (L2P) mapping information stored at a host system, whether data associated with the entry is sequential to other data associated with a next entry or a previous entry. Each entry may have a third field, which may indicate whether the data is sequential. Based on the third field, the host system may determine whether data to be read from a memory system is sequential. The host system may transmit one read command to the memory system if the data is sequential, where the read command may include at least a portion of an L2P entry associated with the data. Similarly, based on the third field, the memory system may determine whether the data to be read is sequential, and may read additional, sequential data if the memory system determines that the data is sequential.

Abstract: Methods, systems, and devices for hardware reset management for universal flash storage (UFS) are described. A UFS device may initiate a boot-up procedure that includes multiple phases. The UFS device may perform a first reset operation to reset one or more circuits based on receiving a first reset command during a first phase. The UFS device perform a second phase and may initiate a portion of a second reset operation to reset the one or more circuits during the second phase based on a likelihood that a second reset command is to be received. The UFS device may receive the second reset command during the second phase after initiating the portion of the second reset operation. The UFS device may initiate a second portion of the second reset operation based on receiving the second reset command and initiating the portion of the second reset operation.

Abstract: Methods, systems, and devices for techniques for detection of shutdown patterns are described. A memory device may receive a set of commands from a host device. The memory device may determine whether the set of commands are associated with a shutdown procedure based on a pattern of the received set of commands. The memory device may initiate one or more operations associated with the shutdown procedure based on identifying that the set of commands are associated with the shutdown procedure. The memory device may receive a shutdown command for the shutdown procedure after initiating the one or more operations associated with the shutdown procedure. The memory device may determine that the set of commands are associated with the shutdown procedure based on a quantity of the set of commands, one or more types of the set of commands, other thresholds associated with the pattern, or a combination thereof.

Abstract: Methods, systems, and devices for commanded device states for a memory system are described. For example, a memory system may be configured with different device states that are each associated with a respective allocation of resources (e.g., feature sets) for operations of the memory system. Resource allocations corresponding to the different device states may be associated with different combinations of memory management configurations, error control configurations, trim parameters, degrees of parallelism, or endurance configurations, among other parameters of the memory system, which may support different tradeoffs between performance characteristics of the memory system. A host system may be configured to evaluate various parameters of operating the host system, and to transmit commands for a memory system to enter a desired device state of the memory system.

Abstract: Methods, systems, and devices for dynamic power modes for boot-up procedures are described. A memory system may initiate a boot-up procedure according to a predefined first power mode that is associated with a first power consumption. The memory system may then determine whether to perform the boot-up procedure according to the first power mode or a second power mode associated with a different second power consumption. In cases that the memory system receives an indication of the second power mode from the host system, the memory system may perform the boot-up procedure according to the second power mode. Additionally, in cases that the memory system does not receive an indication of the second power mode from the host system, the memory system may perform the boot-up procedure according to the first power mode.

Abstract: Methods, systems, and devices are described to indicate, in an entry of logical to physical (L2P) mapping information stored at a host system, whether data associated with the entry is sequential to other data associated with a next entry or a previous entry. Each entry may have a third field, which may indicate whether the data is sequential. Based on the third field, the host system may determine whether data to be read from a memory system is sequential. The host system may transmit one read command to the memory system if the data is sequential, where the read command may include at least a portion of an L2P entry associated with the data. Similarly, based on the third field, the memory system may determine whether the data to be read is sequential, and may read additional, sequential data if the memory system determines that the data is sequential.

Abstract: Embodiment of a method for programming a memory device of the type comprising a matrix of memory cells divided in buffers of cells capacitively uncoupled from each other, the method comprising: first programming of said cells belonging to a buffer; second programming of said cells belonging to said buffer; said step of first programming occurs with a ramp gate voltage having first pitch and programs said cells of said buffer with higher threshold distribution and said step of second programming occurs with a ramp gate voltage having pitch lower than the pitch.

Abstract: A non-volatile memory device includes an array of memory cells organized into a plurality of array sectors, with each array sector being singularly addressable through an array wordline. An array of reference cells is addressable through a reference wordline. A respective voltage ramp generator is provided for each array sector for generating a voltage ramp on an array wordline for reading a memory cell therein, and is provided for each array of reference cells for generating a voltage ramp on a reference wordline for a reference cell therein. A respective row decoding circuit is coupled between each respective voltage ramp generator and corresponding reference wordline or array wordline. A current generator generates a current to be injected on a circuit node in a selected array sector and on a circuit node of the array of reference cells to produce on the circuit nodes a voltage ramp similar to the generated voltage ramp.

Abstract: Embodiment of a method for programming a memory device of the type comprising a matrix of memory cells divided in buffers of cells capacitively uncoupled from each other, the method comprising: first programming of said cells belonging to a buffer; second programming of said cells belonging to said buffer; said step of first programming occurs with a ramp gate voltage having first pitch and programs said cells of said buffer with higher threshold distribution and said step of second programming occurs with a ramp gate voltage having pitch lower than the pitch.

Abstract: A sensing circuit for a semiconductor memory comprising a circuit branch intended to be electrically coupled to a memory bit line having connected thereto a memory cell to be sensed. A bit line precharge circuit is provided, for precharging the memory bit line to a predetermined potential in a precharge phase of a memory cell sensing operation. An evaluation circuit is associated with the memory bit line for evaluating an electric quantity developing on the memory bit line during an evaluation phase of the memory cell sensing operation; the electric quantity that develops on the memory bit line is indicative of an information content of the memory cell. The bit line precharge circuit is adapted to both charging and discharging the memory bit line, so that the predetermined bit line potential is reached irrespective of a memory bit line initial potential at the beginning of the precharge phase.

Abstract: A non-volatile memory device includes an array of memory cells organized into a plurality of array sectors, with each array sector being singularly addressable through an array wordline. An array of reference cells is addressable through a reference wordline. A respective voltage ramp generator is provided for each array sector for generating a voltage ramp on an array wordline for reading a memory cell therein, and is provided for each array of reference cells for generating a voltage ramp on a reference wordline for a reference cell therein. A respective row decoding circuit is coupled between each respective volage ramp generator and corresponding reference wordline or array wordline. A current generator generates a current to be injected on a circuit node in a selected array sector and on a circuit node of the array of reference cells to produce on the circuit nodes a voltage ramp similar to the generated voltage ramp.

Abstract: A sensing circuit for a semiconductor memory comprising a circuit branch intended to be electrically coupled to a memory bit line having connected thereto a memory cell to be sensed. A bit line precharge circuit is provided, for precharging the memory bit line to a predetermined potential in a precharge phase of a memory cell sensing operation. An evaluation circuit is associated with the memory bit line for evaluating an electric quantity developing on the memory bit line during an evaluation phase of the memory cell sensing operation; the electric quantity that develops on the memory bit line is indicative of an information content of the memory cell. The bit line precharge circuit is adapted to both charging and discharging the memory bit line, so that the predetermined bit line potential is reached irrespective of a memory bit line initial potential at the beginning of the precharge phase.