Patents by Inventor Marco Passerini

Marco Passerini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210287747
    Abstract: A switching architecture provides input voltage signals from input voltage lines to a plurality of global word lines connected to word lines of a memory array in a memory device. The switching architecture includes a first switching block receiving a first set of positive voltages used to bias unselected word lines and being connected to a first output line providing a first output bias voltage, and a second switching block receiving a second set of positive voltages and a third set of negative voltages used to bias selected word lines and being connected to a second output line providing a second output bias voltage. A plurality of final switches are input connected to the first and second output lines and are output connected to a respective global word line.
    Type: Application
    Filed: March 9, 2021
    Publication date: September 16, 2021
    Applicant: SK hynix Inc.
    Inventors: Marco Passerini, Giulio Maria Iadicicco, Yong Tae KIM, Moon Soo SUNG, Dario Melchionni, Miriam Sangalli
  • Patent number: 10171098
    Abstract: Disclosed herein is an analog-to-digital converter (ADC) for converting an input analog voltage to an output digital code, the ADC comprising a first node of the input analog voltage; nodes of a plurality of reference voltages; a plurality of comparators, inputs of each comparator being coupled to the first node and a node of a corresponding reference voltage of the plurality of reference voltages; a logic circuit block for receiving outputs of the plurality of comparators and generating the output digital code; and a voltage stabilizer, terminals of the voltage stabilizer being coupled with the first node and a node of a first reference voltage among the plurality of reference voltages.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: January 1, 2019
    Assignee: SK Hynix Inc.
    Inventors: Luigi Paone, Marco Passerini
  • Publication number: 20180145698
    Abstract: Disclosed herein is an analog-to-digital converter (ADC) for converting an input analog voltage to an output digital code, the ADC comprising a first node of the input analog voltage: nodes of a plurality of reference voltages; a plurality of comparators, inputs of each comparator being coupled to the first node and a node of a corresponding reference voltage of the plurality of reference voltages; a logic circuit block for receiving outputs of the plurality of comparators and generating the output digital code; and a voltage stabilizer, terminals of the voltage stabilizer being coupled with the first node and a node of a first reference voltage among the plurality of reference voltages.
    Type: Application
    Filed: November 20, 2017
    Publication date: May 24, 2018
    Inventors: Luigi PAONE, Marco PASSERINI
  • Patent number: 9909931
    Abstract: A temperature sensor includes a first current generating circuit configured to generate a first current being constant regardless of temperature changes, a cascode circuit configured to generate a cascode voltage, a second current generating circuit configured to generate a second current being in inverse proportion to temperature, and a compensated voltage output circuit configured to output a compensated voltage having various temperature coefficients in response to the first current and the second current.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: March 6, 2018
    Assignee: SK HYNIX INC.
    Inventors: Kyu Tae Park, Marco Passerini
  • Patent number: 9571092
    Abstract: Devices and circuits for high voltage switch (HVS) configurations. HVS may pass high voltage without suffering voltage drops. HVS may also guarantee safe operations for p-mos transistors. HVS may not sink current in its steady state. Further, HVS may select between two or more different voltage values to be passed onto the output node even after the high voltage has already been fully developed on the high voltage supply line.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: February 14, 2017
    Assignee: Longitude Semiconductor S.a.r.l.
    Inventors: Marco Passerini, Nicola Maglione
  • Publication number: 20160146677
    Abstract: A temperature sensor includes a first current generating circuit configured to generate a first current being constant regardless of temperature changes, a cascode circuit configured to generate a cascode voltage, a second current generating circuit configured to generate a second current being in inverse proportion to temperature, and a compensated voltage output circuit configured to output a compensated voltage having various temperature coefficients in response to the first current and the second current.
    Type: Application
    Filed: April 24, 2015
    Publication date: May 26, 2016
    Inventors: Kyu Tae PARK, Marco PASSERINI
  • Patent number: 8884666
    Abstract: Disclosed herein is a device comprising a first terminal for a first clock signal, a second terminal for a second clock signal substantially complementary to the first clock signal, a third terminal for a third clock signal, a fourth terminal for a fourth clock signal substantially complementary to the third clock signal, a first logic gate to produce a first intermediate signal, a second logic gate to produce a second intermediate signal, a first delay circuit to produce a third intermediate signal, and a second delay circuit to produce a fourth intermediate signal, and a first output circuit coupled to the first and second delay circuits to produce the third and fourth clock signals respectively at the third and fourth terminals.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: November 11, 2014
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Marco Passerini, Stefano Surico
  • Patent number: 8779811
    Abstract: Disclosed herein is a device comprising a first terminal for a first clock signal, a second terminal for a second clock signal substantially complementary to the first clock signal, a third terminal for a third clock signal, a fourth terminal for a fourth clock signal substantially complementary to the third clock signal, a first logic gate to produce a first intermediate signal, a second logic gate to produce a second intermediate signal, a first delay circuit to produce a third intermediate signal, and a second delay circuit to produce a fourth intermediate signal, and a first output circuit coupled to the first and second delay circuits to produce the third and fourth clock signals respectively at the third and fourth terminals.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: July 15, 2014
    Inventors: Marco Passerini, Stefano Surico
  • Patent number: 8644079
    Abstract: Disclosed here in a method that comprises performing an erase operation on multiple cells in a memory device, the performing comprising applying an erase voltage to the multiple cells, bit lines coupled to the multiple cells being thereby charged up; and discharging the bit lines by coupling the bit lines to a discharging line through a DC path.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: February 4, 2014
    Inventors: Marco Passerini, Simone Bartoli, Osama Khouri
  • Publication number: 20130200941
    Abstract: Devices and circuits for high voltage switch (HVS) configurations. HVS may pass high voltage without suffering voltage drops. HVS may also guarantee safe operations for p-mos transistors. HVS may not sink current in its steady state. Further, HVS may select between two or more different voltage values to be passed onto the output node even after the high voltage has already been fully developed on the high voltage supply line.
    Type: Application
    Filed: February 3, 2012
    Publication date: August 8, 2013
    Applicant: Elpida Memory, Inc.
    Inventors: Marco Passerini, Nicola Maglione
  • Publication number: 20130193590
    Abstract: A semiconductor device includes a first bonding pad, a second bonding pad, a wire bonded to a selected one of the first and second bonding pads, a power supply line electrically connected to the first bonding pad, and a voltage converter circuit coupled to the second bonding pad, the voltage converter circuit being activated when the wire is bonded to the second pad to produce an internal power voltage, which is different from a voltage received by the voltage converter circuit through the wire and the second bonding pad, and supply the internal power voltage to the power supply line, and the voltage converter circuit being deactivated when the wire is connected to the first bonding pad to allow the power supply line to receive a power voltage through the wire and the first bonding pad.
    Type: Application
    Filed: January 31, 2012
    Publication date: August 1, 2013
    Applicant: Elpida Memory, Inc.
    Inventors: Simone Bartoli, Antonino Geraci, Stefano Sivero, Marco Passerini
  • Patent number: 8493137
    Abstract: Devices and circuits for voltage reference architectures that can increase the PSRR parameter by improving the saturation margin for an output transistor. For example, a device can include a current source coupled between a first power supply line and a circuit node, a voltage production circuit coupled between the circuit node and a second power supply line to produce a plurality of voltages respectively at voltage nodes thereof, a multiplexer coupled to the voltage nodes of the voltage production circuit and the output node and configured to select and output one of the voltages to the output node, and a control circuit configured to supply the one of the voltages to the circuit node.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: July 23, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Marco Passerini, Francesco Mannino, Chiara Missiroli
  • Publication number: 20130069715
    Abstract: Devices and circuits for voltage reference architectures that can increase the PSRR parameter by improving the saturation margin for an output transistor. For example, a device can include a current source coupled between a first power supply line and a circuit node, a voltage production circuit coupled between the circuit node and a second power supply line to produce a plurality of voltages respectively at voltage nodes thereof, a multiplexer coupled to the voltage nodes of the voltage production circuit and the output node and configured to select and output one of the voltages to the output node, and a control circuit configured to supply the one of the voltages to the circuit node.
    Type: Application
    Filed: September 16, 2011
    Publication date: March 21, 2013
    Applicant: Elpida Memory, Inc.
    Inventors: Marco Passerini, Francesco Mannino, Chiara Missiroli
  • Publication number: 20130033947
    Abstract: Disclosed herein is a clock generator that comprises a master or first oscillator having an output terminal which provides a master clock signal and at least one slave or second oscillator having an output terminal which provides a slave clock signal, the master and slave oscillators comprising respective time delay stages and latches, the slave oscillator also comprising logic gates connected to the outputs of the latches and configured to logically combine said outputs to generate a slave clock signal having a different phase with respect to a master clock signal.
    Type: Application
    Filed: August 2, 2011
    Publication date: February 7, 2013
    Applicant: Elpida Memory, Inc.
    Inventors: Marco Passerini, Stefano Surico
  • Publication number: 20120287723
    Abstract: Disclosed here in a method that comprises performing an erase operation on multiple cells in a memory device, the performing comprising applying an erase voltage to the multiple cells, bit lines coupled to the multiple cells being thereby charged up; and discharging the bit lines by coupling the bit lines to a discharging line through a DC path.
    Type: Application
    Filed: May 10, 2011
    Publication date: November 15, 2012
    Applicant: Elpida Memory, Inc.
    Inventors: Marco Passerini, Simone BARTOLI, Osama Khouri
  • Patent number: 7983098
    Abstract: An apparatus and method for improving the performance of an electronic device is disclosed. An idle voltage state is introduced by an adaptive voltage generator when providing or removing a high voltage signal from a line or a node in a circuit. The idle state reduces the undesirable effects of switching disturbances caused by sudden voltage changes in a line or node.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: July 19, 2011
    Assignee: Atmel Corporation
    Inventors: Marco Passerini, Stefano Sivero, Andrea Sacco, Monica Marziani
  • Patent number: 7864583
    Abstract: Various embodiments include memory devices and methods having first memory cells and second memory cells coupled to the first memory cells in a string arrangement, first word lines configured to apply a first voltage to gates of the first memory cells during a verify operation of the first memory cells, and second word lines configured to apply a second voltage to gates of the second memory cells during the verify operation.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: January 4, 2011
    Assignee: Atmel Corporation
    Inventors: Stefano Surico, Marco Passerini, Fablo Tassan Caser, Simone Bartoll
  • Patent number: 7769943
    Abstract: A flash memory includes input/output buffers, a memory array having memory cells coupled to the input/output buffers, and row and column decoders, and a voltage-generator circuit coupled to the row and column decoders. A microcontroller is coupled to the command user interface. Switch-instruction circuitry selectively provides instructions to the microcontroller from the read-only memory and from off chip through on-board t-latches coupled to the input/output buffers under control of a command user interface.
    Type: Grant
    Filed: April 4, 2007
    Date of Patent: August 3, 2010
    Assignee: Atmel Corporation
    Inventors: Stefano Surico, Stefano Sivero, Simone Bartoli, Marco Passerini
  • Publication number: 20100074030
    Abstract: An apparatus and method for improving the performance of an electronic device is disclosed. An idle voltage state is introduced by an adaptive voltage generator when providing or removing a high voltage signal from a line or a node in a circuit. The idle state reduces the undesirable effects of switching disturbances caused by sudden voltage changes in a line or node.
    Type: Application
    Filed: September 30, 2009
    Publication date: March 25, 2010
    Applicant: Atmel Corporation
    Inventors: Marco Passerini, Stefano Sivero, Andrea Sacco, Monica Marziani
  • Patent number: 7599231
    Abstract: An apparatus and method for improving the performance of an electronic device is disclosed. An idle voltage state is introduced by an adaptive voltage generator when providing or removing a high voltage signal from a line or a node in a circuit. The idle state reduces the undesirable effects of switching disturbances caused by sudden voltage changes in a line or node.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: October 6, 2009
    Assignee: Atmel Corporation
    Inventors: Marco Passerini, Stefano Sivero, Andrea Sacco, Monica Marziani