Abstract: The invention relates to a method of routing or compressing packets destination address through an electronic routing or compressing device, the packets destination address being n bit packets and having address indicative of a desired destination, the address being classless, the routing device having at least a data base of prefix entries, each of which containing entries corresponding to a desired output data link, the method having the steps of: a) generating an address mask until an entry matching a masked address obtained by making an AND operation between the packets destination address and the address mask, is found in the data; the address mask having a number of bit equal to that of the packets destination address and having, starting from the most significant n-bit equal to 1 and the remaining i bit equal to 0, with 0<=u<=b.

Abstract: A distributed interface between a microprocessor or a standard bus and user macro-cells belonging to an ASIC, FPGA, or similar silicon devices includes a main module connected to the microprocessor bus on one side and to a COMMON-BUS inside the interface on which a cluster of peripheral modules is appended on the other side. Peripheral modules are also connected to the user macro-cells through multiple point-to-point buses to transfer signals in two directions. A set of hardware and firmware resources such as registers, counters, synchronizers, dual port memories (e.g. RAM, FIFO) either synchronous or asynchronous with respect to macro-cells clock is encompassed in each peripheral module. Subsets of the standard resources are diversely configured in each peripheral module in accordance with specific needs of the user macro-cells.

Abstract: A clock signal generation and distribution system for a prototyping apparatus of an electronic system comprises at least one clock signal generation and distribution subsystem for distributing at least one clock signal to the prototyped electronic system implemented by the prototyping apparatus through a clock signal distribution network of the prototyping apparatus. The at least one clock signal generation and distribution subsystem comprises a clock source selector for selecting the at least one clock signal to be distributed to the prototyped electronic system among a group of source clock signals, the group including at least one first source clock signal derived from the prototyped electronic system and at least one second source clock signal not derived from the prototyped electronic system.

Abstract: A distributed interface between a microprocessor or a standard bus and user macro-cells belonging to an ASIC, or FPGA, or similar silicon devices includes a main module connected to the microprocessor bus on one side and to a COMMON-BUS inside the interface on which a cluster of peripheral modules is appended on the other side. Peripheral modules are also connected to the user macro-cells through as multiple point-to-point buses to transfer signals two directions. A set of hardware and firmware resources such as registers, counters, synchronizers, dual port memories (e.g. RAM, FIFO) either synchronous or asynchronous with respect to macro-cells clock is encompassed in each peripheral module. Subsets of the standard resources are diversely configured in each peripheral module in accordance with specific needs of the user macro-cells.

Abstract: A daughter board (405) is provided for a prototyping system (100). The daughter board includes a first surface for facing a mother board (115) of the prototyping system, and a second surface opposed thereto. The daughter board further includes a connector (410) for a corresponding socket (210) of the mother board arranged on the first surface. The connector includes multiple elements (410t-410b), each one including an insulating support and multiple leads. The daughter board also includes multiple contacts (482) for corresponding functional terminals of a programmable device (420) arranged on the second surface. Each contact is connected to a corresponding lead (476) of the connector. The elements of the connector are arranged along the edges of a regular polygon.

Abstract: A distributed interface between a microprocessor or a standard bus and user macro-cells belonging to an ASIC, FPGA, or similar silicon devices includes a main module connected to the microprocessor bus on one side and to a COMMON-BUS inside the interface on which a cluster of peripheral modules is appended on the other side. Peripheral modules are also connected to the user macro-cells through multiple point-to-point buses to transfer signals in two directions. A set of hardware and firmware resources such as registers, counters, synchronizers, dual port memories (e.g. RAM, FIFO) either synchronous or asynchronous with respect to macro-cells clock is encompassed in each peripheral module. Subsets of the standard resources are diversely configured in each peripheral module in accordance with specific needs of the user macro-cells.

Abstract: A daughter board (405) for a prototyping system (100) having a first surface for facing a mother board (115) of the prototyping system and a second surface opposed thereto and including a connector (410) for a corresponding socket (210) of the mother board arranged on the first surface, the connector consisting of a plurality of elements (410t-410b) each one including an insulating support and a plurality of leads, and a plurality of contacts (482) for corresponding functional terminals of a programmable device (420) arranged on the second surface, each contact being connected to a corresponding lead (476) of the connector, wherein the elements of the connector are arranged along the edges of a regular polygon.

Abstract: A distributed interface between a microprocessor, or a standard bus, and user macro-cells belonging to an ASIC, or FPGA, or similar silicon devices is disclosed. The interface consists of a main module connected to the microprocessor bus, at one side, and to a COMMON-BUS inside the interface on which a cluster of peripheral modules is appended, at the other side. Peripheral modules are further connected to the user macro-cells through as many point-to-point buses as the implemented macro-cells, in order to transfer signals in the two directions. A set of hardware and firmware resources comprehensive of the most popular needs of the user macro-cells, like: registers, counters, synchronizers, dual port memories both of RAM and FIFO type either synchronous or asynchronous with respect to macro-cells clock, etc., is encompassed in each peripheral module.

Abstract: A clock signal generation and distribution system for a prototyping apparatus of an electronic system comprises at least one clock signal generation and distribution subsystem for distributing at least one clock signal to the prototyped electronic system implemented by the prototyping apparatus through a clock signal distribution network of the prototyping apparatus. The at least one clock signal generation and distribution subsystem comprises a clock source selector for selecting the at least one clock signal to be distributed to the prototyped electronic system among a group of source clock signals, the group including at least one first source clock signal derived from the prototyped electronic system and at least one second source clock signal not derived from the prototyped electronic system.

Abstract: It is disclosed an algorithm able to compress a defined set of addresses S, the set of addresses to be compressed, belonging to the set U, the whole addressing space; for each of these addresses the algorithm must identify one and only one address belonging to C, the set of compressed address (i.e. perform a transformation S→C). The algorithm may be implemented using some low-cost random access memories (RAM) and some control logic. A performance comparison shows that is possible to perform the address compression using one order of magnitude less memory respect to the state-of-the-art techniques. Basically, the method of the invention combines the splitting of the incoming address space (U) into a plurality of sub-spaces, a tree search algorithm for clustering a defined set (S) of identifiers contained in the sub-spaces into which the incoming addresses space (U) has been split and a sequential search performed within the right cluster in order to identify the compressed address belonging to space C.