Abstract: A high electron mobility transistor comprising: an epitaxial substrate comprising a semi-insulating substrate, a buffer layer and a barrier layer sequentially stacked; a first and a second current conducting electrode formed on, and in ohmic contact with, the barrier layer; a control gate and one or more field plate electrode(s) formed on, and in contact with, the barrier layer between the first and second current conducting electrodes; and an electric circuit formed for electrically connecting each field plate electrode to an electric reference potential and comprising at least a rectifying contact and/or an electric resistor, wherein the rectifying contact is formed outside the channel area of the high electron mobility transistor and is distinguished from the rectifying contact formed by the corresponding field plate electrode.

Abstract: Disclosed is a vertical PIN diode having: an N-type layer; a cathode contact formed on a first portion of the N-type layer defining a cathode region; an intrinsic layer formed on a second portion of the N-type layer; a portion of a P-type layer formed on a first portion of the intrinsic layer and defining an anode region; an anode contact formed on the portion of the P-type layer defining the anode region; and a protection structure formed on a second portion of the intrinsic layer to laterally protect the portion of the P-type layer defining the anode region from an etching intended to expose the first portion of the N-type layer defining the cathode region, wherein the protection structure is formed by implanting ions in a further portion of the P-type layer, which laterally surrounds the portion of the P-type layer defining the anode region.

Abstract: Disclosed is a vertical PIN diode having: an N-type layer; a cathode contact formed on a first portion of the N-type layer defining a cathode region; an intrinsic layer formed on a second portion of the N-type layer; a portion of a P-type layer formed on a first portion of the intrinsic layer and defining an anode region; an anode contact formed on the portion of the P-type layer defining the anode region; and a protection structure formed on a second portion of the intrinsic layer to laterally protect the portion of the P-type layer defining the anode region from an etching intended to expose the first portion of the N-type layer defining the cathode region, wherein the protection structure is formed by implanting ions in a further portion of the P-type layer, which laterally surrounds the portion of the P-type layer defining the anode region.

Abstract: The invention concerns a method of manufacturing a vertical PIN diode comprising: providing an epitaxial wafer comprising a vertically stacked N-type layer, intrinsic layer and P-type layer; forming an anode contact of the vertical PIN diode by forming an anode metallization on a first portion of the P-type layer defining an anode region; forming an electrically insulating layer around the anode region such that a first portion of the intrinsic layer extends vertically between the N-type layer and the anode region and second portions of the intrinsic layer extend vertically between the N-type layer and the electrically insulating layer; forming a trench in the electrically insulating layer and in the second portions of the intrinsic layer so as to expose a portion of the N-type layer defining a cathode region and to define a sacrificial side-guard ring consisting of a portion of the electrically insulating layer that extends laterally between the trench and the anode region and laterally surrounds said anode

Abstract: A high electron mobility transistor comprising: an epitaxial substrate comprising a semi-insulating substrate, a buffer layer and a barrier layer sequentially stacked; a first and a second current conducting electrode formed on, and in ohmic contact with, the barrier layer; a control gate and one or more field plate electrode(s) formed on, and in contact with, the barrier layer between the first and second current conducting electrodes; and an electric circuit formed for electrically connecting each field plate electrode to an electric reference potential and comprising at least a rectifying contact and/or an electric resistor, wherein the rectifying contact is formed outside the channel area of the high electron mobility transistor and is distinguished from the rectifying contact formed by the corresponding field plate electrode.

Abstract: A process of manufacturing a high electron mobility transistor, comprising: providing an epitaxial substrate comprising a semi-insulating substrate, a buffer layer and a barrier layer sequentially stacked; forming a first and second current conducting electrodes formed on, and in ohmic contact with, the barrier layer; and forming a control gate on, and in Schottky contact with, the barrier layer, between the first and second current conducting electrodes. The control gate is formed on the barrier layer by initially forming a lower portion of the control gate, then performing a thermal stabilization and annealing treatment to remove the damage to the crystal lattice of the surface of the semiconductor introduced by the preceding process steps and stabilize the metal-semiconductor interface of the Schottky junction, and finally forming an upper portion of the control gate on, and in electric contact with, the lower portion of the control gate.

Abstract: Disclosed herein is a pseudomorphic high electron mobility transistor (PHEMT) power device (1) including a semi-insulating substrate (2); an epitaxial substrate (3) formed on the semi-insulating substrate (2) a contact layer (19). The contact layer (19) includes a lightly doped contact layer (20) formed on the Schottky layer (18), and a highly doped contact layer (21) formed on the lightly doped contact layer (20) and having a doping concentration higher than the lightly doped contact layer (20). The PHEMT power device (1) further includes a—wide recess (23) formed to penetrate the highly doped contact layer (21) and a narrow recess (24) formed in the wide recess (23) to penetrate the lightly doped contact layer (20). The gate electrode (6) is formed in the narrow recess (24) and in Schottky contact with the Schottky layer (18).

Abstract: The invention concerns a method of manufacturing a vertical PIN diode comprising: providing an epitaxial wafer comprising a vertically stacked N-type layer, intrinsic layer and P-type layer; forming an anode contact of the vertical PIN diode by forming an anode metallization on a first portion of the P-type layer defining an anode region; forming an electrically insulating layer around the anode region such that a first portion of the intrinsic layer extends vertically between the N-type layer and the anode region and second portions of the intrinsic layer extend vertically between the N-type layer and the electrically insulating layer; forming a trench in the electrically insulating layer and in the second portions of the intrinsic layer so as to expose a portion of the N-type layer defining a cathode region and to define a sacrificial side-guard ring consisting of a portion of the electrically insulating layer that extends laterally between the trench and the anode region and laterally surrounds said anode

Abstract: Disclosed herein is a pseudomorphic high electron mobility transistor (PHEMT) power device (1) including a semi-insulating substrate (2); an epitaxial substrate (3) formed on the semi-insulating substrate (2) a contact layer (19). The contact layer (19) includes a lightly doped contact layer (20) formed on the Schottky layer (18), and a highly doped contact layer (21) formed on the lightly doped contact layer (20) and having a doping concentration higher than the lightly doped contact layer (20). The PHEMT power device (1) further includes a—wide recess (23) formed to penetrate the highly doped contact layer (21) and a narrow recess (24) formed in the wide recess (23) to penetrate the lightly doped contact layer (20). The gate electrode (6) is formed in the narrow recess (24) and in Schottky contact with the Schottky layer (18).