Abstract: Implementations described herein relate to a cluster namespace for a memory device. In some implementations, a memory device may receive a cluster namespace instruction, from a host device, that instructs the memory device to create a cluster namespace using memory resources of the memory device that are spread across a plurality of namespaces of the memory device. The memory device may identify namespace storage information that indicates memory resources associated with a plurality of namespaces of the memory device. The memory device may create the cluster namespace based on creating a plurality of extents that respectively map sets of logical block address ranges from the plurality of namespaces to the cluster namespace.

Abstract: Methods, systems, and devices for multi-host communications are described. In some examples, a memory system may be coupled with multiple host systems. The memory system may facilitate communications between the multiple host systems For example, a first host system may be coupled with a first buffer of the memory system and a second host system may be coupled with a second buffer of the memory system. The first host system may have read and write access to the first buffer and read access to the second buffer. In response to a write operation being initiated by the first host system, data may be written to the first buffer. The second host system may read the data written to the first buffer. The second host system may take an action or respond based on the data read from the first buffer.

Abstract: A memory device controller for a non-volatile memory device can be configured to allow exclusive access to initiate or increment a refresh routine based on an earlier-received one of a refresh command from a host device or an interval-triggered refresh command from the controller. The memory device controller can be configured to lock out access to the refresh routine from a later-received one of the refresh command from the host device or the interval-triggered refresh command from the controller. The memory device controller can release a lock on access to the refresh routine upon completion of a block refresh routine for a memory block of the memory device. In some examples, the refresh command from the host device can be based on a power cycle status of the host device.

Abstract: Implementations described herein relate to selective data map unit access. A memory device may receive a request from a host device to access a resource associated with a data map unit. The memory device may identify whether the data map unit is in a locked state or an unlocked state. The data map unit may be in the locked state when another host device currently has exclusive access to the resource or may be in the unlocked state when no other host device currently has exclusive access to the resource. The memory device may selectively grant the host device exclusive access to the resource based on identifying whether the data map unit is in the locked state or the unlocked state.

Abstract: An example system includes a processing resource and a switch board coupled to a system under test (SUT) and the processing resource. The SUT includes a memory device. The switch board can be configured to provide power to the SUT, communicate a first signal from the SUT to the processing resource, and provide a second signal to the SUT that simulates an input to the SUT during operation of the SUT. The processing resource can be configured to receive a function, selected from a library of functions, to execute during a test of the memory device and cause the switch board to provide the second signal during the test of the SUT.

Abstract: An example apparatus includes a first memory and a second memory coupled to the first memory. A controller may be coupled to the first memory and the second memory. The controller may be configured to cause the apparatus to be initialized by executing instructions on the first memory device. Initializing the apparatus may include operating the apparatus according to a set of semantics different than a set of semantics used by the second memory device. The controller may be configured to cause a determination regarding at least one health characteristic of the second memory to be made subsequent to the apparatus being initialized.

Abstract: An example system includes a processing resource and a switch board coupled to a system under test (SUT) and the processing resource. The SUT includes a memory device. The switch board can be configured to provide power to the SUT, communicate a first signal from the SUT to the processing resource, and provide a second signal to the SUT that simulates an input to the SUT during operation of the SUT. The processing resource can be configured to receive a function, selected from a library of functions, to execute during a test of the memory device and cause the switch board to provide the second signal during the test of the SUT.

Abstract: An example system includes a processing resource and a switch board coupled to a system under test (SUT) and the processing resource. The SUT includes a memory device. The switch board can be configured to provide power to the SUT, communicate a first signal from the SUT to the processing resource, and provide a second signal to the SUT that simulates an input to the SUT during operation of the SUT. The processing resource can be configured to receive a function, selected from a library of functions, to execute during a test of the memory device and cause the switch board to provide the second signal during the test of the SUT.

Abstract: An example apparatus includes a first memory and a second memory coupled to the first memory. A controller may be coupled to the first memory and the second memory. The controller may be configured to cause the apparatus to be initialized by executing instructions on the first memory device. Initializing the apparatus may include operating the apparatus according to a set of semantics different than a set of semantics used by the second memory device. The controller may be configured to cause a determination regarding at least one health characteristic of the second memory to be made subsequent to the apparatus being initialized.

Abstract: An example system includes a processing resource and a switch board coupled to a system under test (SUT) and the processing resource. The SUT includes a memory device. The switch board can be configured to provide power to the SUT, communicate a first signal from the SUT to the processing resource, and provide a second signal to the SUT that simulates an input to the SUT during operation of the SUT. The processing resource can be configured to receive a function, selected from a library of functions, to execute during a test of the memory device and cause the switch board to provide the second signal during the test of the SUT.

Abstract: An example apparatus includes a first memory and a second memory coupled to the first memory. A controller may be coupled to the first memory and the second memory. The controller may be configured to cause the apparatus to be initialized by executing instructions on the first memory device. Initializing the apparatus may include operating the apparatus according to a set of semantics different than a set of semantics used by the second memory device. The controller may be configured to cause a determination regarding at least one health characteristic of the second memory to be made subsequent to the apparatus being initialized.

Abstract: An example apparatus includes a first memory and a second memory coupled to the first memory. A controller may be coupled to the first memory and the second memory. The controller may be configured to cause the apparatus to be initialized by executing instructions on the first memory device. Initializing the apparatus may include operating the apparatus according to a set of semantics different than a set of semantics used by the second memory device. The controller may be configured to cause a determination regarding at least one health characteristic of the second memory to be made subsequent to the apparatus being initialized.

Abstract: A NAND-type flash memory device is described. In some embodiments, the memory device includes NAND-type flash memory cells, and a synchronous NAND interface. The synchronous NAND interface includes a standard NAND flash interface pin arrangement and a clock (CLK) pin. The synchronous NAND interface is configured to interface with a NOR-compatible memory interface.

Abstract: A NAND-type flash memory device is described. In some embodiments, the memory device includes NAND-type flash memory cells, and a synchronous NAND interface. The synchronous NAND interface includes a standard NAND flash interface pin arrangement and a clock (CLK) pin. The synchronous NAND interface is configured to interface with a NOR-compatible memory interface.

Abstract: A machine for packaging products (13) in sealed film (25), comprises a product inlet feeding bench (12), a rotating head (15) for receiving and conveying products arriving sequentially from the feeding bench to a loading station (14) in the head and an outlet bench (17) that receives the products conveyed by the rotating head (15) to an unloading station (16) to evacuate them from the machine. The rotating head (15) comprises peripherally seats (30, 31) for receiving products and a sealing device (45, 46, 47, 48) that rotates with these seats (30, 31) to achieve sealing of a film wound around the product in a seat (30, 31) whilst the head rotates to take the seat (30, 31) from the loading station (14) to the unloading station (31).

Abstract: A machine for packaging products (13) in sealed film (25), comprises a product inlet feeding bench (12), a rotating head (15) for receiving and conveying products arriving sequentially from the feeding bench to a loading station (14) in the head and an outlet bench (17) that receives the products conveyed by the rotating head (15) to an unloading station (16) to evacuate them from the machine. The rotating head (15) comprises peripherally seats (30, 31) for receiving products and sealing means (45, 46, 47, 48) that rotates with these seats (30, 31) to achieve sealing of a film wound around the product in a seat (30, 31) whilst the head rotates to take the seat (30, 31) from the loading station (14) to the unloading station (31).

Abstract: An integrated circuit memory device and a method of providing access to multiple memory types within a single integrated circuit memory device are described. In various embodiments, the integrated circuit memory device includes a non-volatile memory array having a first emulated memory region and a second emulated memory region, and a controller having an interface. The memory device is configured to emulate a first emulated memory type and a second emulated memory type. The memory device is further configured to store data in the first emulated memory region when the memory device emulates the first emulated memory type, and in the second emulated memory region when the memory device emulates the second emulated memory type.

Abstract: A non-volatile semiconductor memory device is provided comprising a memory area and a circuitry area. The memory area includes a plurality of memory cells and a set of array reference cells that are programmable to have a threshold voltage corresponding to an erased or a programmed state of a memory cell. In the circuitry area, additional main reference cells are provided, which are configured to also have a threshold voltage corresponding to an erased or programmed state of a memory cell. The main reference cells are used for setting of said array reference cells and said array reference cells are provided as a reference for reading or writing a state of said memory cells. A method is also provided for setting array reference cells in a non-volatile semiconductor memory device to a predefined threshold voltage.

Abstract: A method of sensing a state of a non-volatile semiconductor memory cell is provided. A memory cell current as well as a comparative current generated from at least one reference cell are compared with a predefined reference current while the gate voltages of the cells are varied. Sense amplifiers detect which of said currents first reaches the predefined reference current. The order of reaching the reference current is indicative of the state of the memory cell. In a preferred embodiment of the invention the comparative current is generated as an average of an erased reference cell current and a programmed reference cell current.

Abstract: A non-volatile memory device is proposed. The non-volatile memory device includes a flash memory and means for executing external commands, the external commands including a first subset of commands for accessing the flash memory directly; the memory device further includes a programmable logic unit and means for storing program code for the logic unit, the external commands including a second subset of at least one command for causing the logic unit to process information stored in at least one portion of the flash memory under the control of the program code.