Abstract: Implementations described herein relate to host device initiated low temperature thermal throttling. A memory device may receive, from a host device, a low temperature thermal throttling command that indicates for the memory device to initiate a thermal throttling operation based on a temperature of the memory device not satisfying a temperature threshold. The low temperature thermal throttling command may indicate an amount of dummy data to be moved from the host device to a particular location of the memory device associated with the thermal throttling operation. The memory device may perform the thermal throttling operation based on moving the dummy data from the host device to the particular location of the memory device. The memory device may complete the thermal throttling operation based on moving the amount of data from the host device to the particular location of the memory device.

Abstract: Implementations described herein relate to memory device initialization. In some implementations, a memory device may perform a first initialization for a first set of memory resources, the first initialization being associated with a boot image initialization. The memory device may enable a sideband interface, for data transfer between the memory device and a host device, based on a completion of the first initialization. The memory device may perform a second initialization for a second set of memory resources that is larger than the first set of memory resources. The memory device may enable a peripheral component interconnect express interface, for data transfer between the memory device and the host device, based on a completion of the second initialization.

Abstract: A memory sub-system includes a non-volatile memory (NVM) memory device and a processing device operatively coupled to the memory device and to a host system. The processing device includes embedded volatile memory and retrieves, in response to power on of the memory sub-system, a read-only memory (ROM) code from an internal ROM of the processing device. The processing device executes the ROM code to load a boot code, from the memory device, into the embedded volatile memory. The processing device executes the boot code to load a first stage firmware into the embedded volatile memory. The first stage firmware is to enable access to a boot partition of the memory device before the processing device has full operational access to the memory device.

Abstract: Implementations described herein relate to abrupt power loss management. In some implementations, a memory device may receive a peripheral component interconnect express reset (PERST) signal. The memory device may perform a write protect operation based on receiving the PERST signal. The memory device may initiate a reduced power consumption state of the memory device based on a completion of the write protect operation.

Abstract: Implementations described herein relate to emergency data storing operation selection. In some implementations, a memory device may be configured to receive a peripheral component interconnect power loss notification (PLN) signal and a peripheral component interconnect express reset (PERST) signal. The memory device may be configured to determine whether to initiate a first data storing operation or a second data storing operation based on the PERST signal state based on a falling edge of the PLN signal. The memory device may be configured to selectively initiate the first data storing operation or the second data storing operation. The first data storing operation may include storing data associated with the memory device prior to the memory device experiencing a power loss, and the second data storing operation may include storing data and metadata associated with the memory device prior to the memory device experiencing the power loss.

Abstract: Methods, systems, and apparatuses include receiving, by a memory subsystem, an activate command for firmware of the memory subsystem, where the firmware includes a core firmware subportion and a diagnostic firmware subportion, content of the diagnostic firmware subportion differs from content of the core firmware subportion, and the diagnostic firmware subportion and the core firmware subportion execute independently of one another. The core firmware subportion is activated causing the memory subsystem to operate using the core firmware subportion in response to the received activate command. The diagnostic firmware subportion is deactivated preventing the memory subsystem from operating using the diagnostic firmware subportion in response to the received activate command.

Abstract: A system includes an integrated circuit (IC) memory device with memory cells. A volatile memory device includes a queue to store indicators for one or more blocks of the memory cells that are to be refreshed. A processing device is operatively coupled to the IC memory device and the volatile memory device. The processing device detects initiation of a power-down operation of the system. In response to detecting the initiation of the power-down operation, the processing devices detects one or more indicators remain in the queue corresponding to the one or more blocks and sends a signal to a host system coupled to the processing device. The signal indicates to the host system to wait to complete the power-down operation until writing refresh data, from the one or more blocks, to one or more erased blocks of the IC memory device is complete.

Abstract: Implementations described herein relate to a two-stage emergency data storing operation. In some implementations, a memory device may detect a power loss notification signal that indicates a power loss condition of the memory device. The memory device may read a mode register bit of the memory device that indicates to perform a data storing operation that includes a first data storing stage and a second data storing stage. The first data storing stage may include storing data associated with the memory device prior to the memory device experiencing a power loss, and the second data storing stage may include storing data and metadata associated with the memory device prior to the memory device experiencing the power loss. The memory device may initiate the data storing operation and may selectively acknowledge the power loss condition based on completing the first data storing stage or the second data storing stage.

Abstract: Methods, systems, and devices for sorting retired blocks of non-volatile memory cells are described. A memory system may recover a block that has been marked as “bad” using a requalification process. For example, after operating in an error protection mode for the block, the memory system may monitor the block to determine whether a status flag indicating an access error is set. If the status flag is set, the memory system may store information that indicates the block is unrecoverable, and the block may subsequently be retired. Alternatively, if a status flag is not set, the memory system may store information that indicates the block may be recoverable. If one or more additional access operations to the block are successful, the memory system may store information that indicates the block may be used for subsequent access operations.

Abstract: Implementations described herein relate to a power hold-off circuit and power hold-off circuit operation. In some implementations, a system may include a battery, and a power hold-off circuit. The power hold-off circuit may include a step-up regulator, a step-down regulator, a first abrupt power-loss (APL) switch, a second APL switch, and one or more power hold-off capacitors. The system may include a third APL switch between the battery and the power hold-off circuit. The third APL switch and the first APL switch may be in a closed state, and the second APL switch may be connected to the step-up regulator, when a voltage from the battery satisfies a voltage threshold. The third APL switch and the first APL switch may be in an open state, and the second APL switch may be connected to the step-down regulator, when the voltage from the battery does not satisfy the voltage threshold.

Abstract: Methods, systems, and devices for multi-host communications are described. In some examples, a memory system may be coupled with multiple host systems. The memory system may facilitate communications between the multiple host systems For example, a first host system may be coupled with a first buffer of the memory system and a second host system may be coupled with a second buffer of the memory system. The first host system may have read and write access to the first buffer and read access to the second buffer. In response to a write operation being initiated by the first host system, data may be written to the first buffer. The second host system may read the data written to the first buffer. The second host system may take an action or respond based on the data read from the first buffer.

Abstract: Implementations described herein relate to a cluster namespace for a memory device. In some implementations, a memory device may receive a cluster namespace instruction, from a host device, that instructs the memory device to create a cluster namespace using memory resources of the memory device that are spread across a plurality of namespaces of the memory device. The memory device may identify namespace storage information that indicates memory resources associated with a plurality of namespaces of the memory device. The memory device may create the cluster namespace based on creating a plurality of extents that respectively map sets of logical block address ranges from the plurality of namespaces to the cluster namespace.

Abstract: Implementations described herein relate to selective data map unit access. A memory device may receive a request from a host device to access a resource associated with a data map unit. The memory device may identify whether the data map unit is in a locked state or an unlocked state. The data map unit may be in the locked state when another host device currently has exclusive access to the resource or may be in the unlocked state when no other host device currently has exclusive access to the resource. The memory device may selectively grant the host device exclusive access to the resource based on identifying whether the data map unit is in the locked state or the unlocked state.

Abstract: Implementations described herein relate to memory device background operations. In some implementations, a memory device may receive a background operation command, from a host device, that indicates for the memory device to initiate a background operation for a memory of the memory device. The background operation command may include at least one of an optimization indicator, an idle time indicator, or a power-off time indicator. The memory device may initiate the background operation in accordance with the background operation command.

Abstract: Implementations described herein relate to memory device initialization. In some implementations, a memory device may perform a first initialization for a first set of memory resources, the first initialization being associated with a boot image initialization. The memory device may enable a sideband interface, for data transfer between the memory device and a host device, based on a completion of the first initialization. The memory device may perform a second initialization for a second set of memory resources that is larger than the first set of memory resources. The memory device may enable a peripheral component interconnect express interface, for data transfer between the memory device and the host device, based on a completion of the second initialization.

Abstract: Various examples are directed to systems and methods involving a managed NAND non-volatile memory device comprising a memory array and a memory controller. The memory controller may receive a verification request from a requesting device, the verification request comprising an indication of a first portion of the memory array, and a first known check value. The memory controller may apply an operation based at least in part on first data from the first portion of the memory array to generate a calculated check value and determine verification result data based at least in part on the first known check value and the calculated check value.

Abstract: A memory device controller for a non-volatile memory device can be configured to allow exclusive access to initiate or increment a refresh routine based on an earlier-received one of a refresh command from a host device or an interval-triggered refresh command from the controller. The memory device controller can be configured to lock out access to the refresh routine from a later-received one of the refresh command from the host device or the interval-triggered refresh command from the controller. The memory device controller can release a lock on access to the refresh routine upon completion of a block refresh routine for a memory block of the memory device. In some examples, the refresh command from the host device can be based on a power cycle status of the host device.

Abstract: An embedded system includes a host device that includes a first peripheral component interconnect express (PCIe) interface; a non-volatile memory (NVM) device that includes a second PCIe interface; and a PCIe bus directly coupled to the first PCIe interface and the second PCIe interface for transmitting direct communications between the host device and the monolithic NVM device.

Abstract: Methods, systems, and devices for multi-host communications are described. In some examples, a memory system may be coupled with multiple host systems. The memory system may facilitate communications between the multiple host systems For example, a first host system may be coupled with a first buffer of the memory system and a second host system may be coupled with a second buffer of the memory system. The first host system may have read and write access to the first buffer and read access to the second buffer. In response to a write operation being initiated by the first host system, data may be written to the first buffer. The second host system may read the data written to the first buffer. The second host system may take an action or respond based on the data read from the first buffer.

Abstract: Implementations described herein relate to selective data map unit access. A memory device may receive a request from a host device to access a resource associated with a data map unit. The memory device may identify whether the data map unit is in a locked state or an unlocked state. The data map unit may be in the locked state when another host device currently has exclusive access to the resource or may be in the unlocked state when no other host device currently has exclusive access to the resource. The memory device may selectively grant the host device exclusive access to the resource based on identifying whether the data map unit is in the locked state or the unlocked state.