Abstract: An intervertebral implant (100) for the fusion between two vertebral bodies of a vertebral column comprising: —a fusion cage (1), extending from a posterior side to an anterior side, adapted to be interposed between two adjacent vertebral bodies of a patient; —an asymmetrical fixing plate (2), attached to the fusion cage (1) and having a plurality of passageways (16; 7) for the insertion of bone screws on a single side.

Abstract: An Intervertebral implant (100) for the fusion between two vertebral bodies of a vertebral column comprising: an internally hollow fusion cage (1); a fixing plate (2); and cooperating features (8, 10, 17, 19, 20, 21) for fastening said fixing plate (2) on the anterior side of the fusion cage (1); the cooperating features (8, 10, 17, 19, 20, 21) comprising restraining means (8, 17) meant to restrain the fixing plate (2) in a posterior-anterior direction with respect to the fusion cage (1) and pivoting means (10, 19) being arranged to guide a rotation, about a pivot axis (x), of said fixing plate (2) with respect to said fusion cage (1).

Abstract: An intervertebral implant (100) for the fusion between two vertebral bodies of a vertebral column comprising: —a fusion cage (1), extending from a posterior side to an anterior side, adapted to be interposed between two adjacent vertebral bodies of a patient; —an asymmetrical fixing plate (2), attached to the fusion cage (1) and having a plurality of passageways (16; 7) for the insertion of bone screws on a single side.

Abstract: Methods and devices for selection and/or isolation of memory cells include use of a thyristor For example, a memory storage component may be selected for access, at least in part, by initiating application of a triggering potential to affect a gate of a thyristor that is coupled in series with a memory storage component. The gate of the thyristor connects to a memory cell word line and permits an efficient polarity scheme for selected and unselected memory array conductors to reduce leakage current relative to conventional selectors, such as bipolar junction transistors.

Abstract: A driver circuit and integrated circuit implementation of a driver circuit for driving a GaN HFET device is disclosed. The driver circuit includes a resonant drive circuit having an LC circuit with an inductance and a capacitance. The capacitance of the LC circuit includes the gate-source capacitance of the GaN HFET device. The driver circuit further includes a level shifter circuit configured to receive a first signal and to amplify the first signal to a second signal suitable for driving a GaN HFET device. The resonant drive circuit is controlled based at least in part on the second signal such that the resonant drive circuit provides a first voltage to the GaN HFET device to control the GaN HFET device to operate in a conducting state and to provide a second voltage to the GaN HFET device to control the GaN HFET device to operate in a non-conducting state.

Abstract: A driver circuit and integrated circuit implementation of a driver circuit for driving a GaN HFET device is disclosed. The driver circuit includes a resonant drive circuit having an LC circuit with an inductance and a capacitance. The capacitance of the LC circuit includes the gate-source capacitance of the GaN HFET device. The driver circuit further includes a level shifter circuit configured to receive a first signal and to amplify the first signal to a second signal suitable for driving a GaN HFET device. The resonant drive circuit is controlled based at least in part on the second signal such that the resonant drive circuit provides a first voltage to the GaN HFET device to control the GaN HFET device to operate in a conducting state and to provide a second voltage to the GaN HFET device to control the GaN HFET device to operate in a non-conducting state.

Abstract: A method for programming a non-volatile memory device of the multi-level type, includes a plurality of transistor cells grouped into memory words and conventionally provided with gate and drain terminals. The method applies different drain voltage values at different threshold values. Such values are directly proportional to the threshold levels to be attained by the individual memory word bits, and effective to provide for a simultaneous attainment of the levels, in a seeking-to manner, of the levels at the end of a limited number of pulses. Advantageously, a constant gate voltage value is concurrently applied to the gate terminals of said cells, such that the cell programming time is unrelated to the threshold level sought.

Abstract: A decoupling circuit for decoupling conduction lines from each other, the circuit including at least one pass gate element having conduction terminals connected to the conduction lines and having at least one control terminal. The decoupling circuit includes at least one protection circuit inserted between the control terminal and at least one of the conduction lines, and including at least one protection transistor connected to the control terminal and to the at least one conduction line, and configured to take in a disturbing signal passing through the pass gate element (N1) to properly decouple the conduction lines from each other on the occurrence of a disturbing condition.

Abstract: A method for programming a non-volatile memory device of the multi-level type, includes a plurality of transistor cells grouped into memory words and conventionally provided with gate and drain terminals. The method applies different drain voltage values at different threshold values. Such values are directly proportional to the threshold levels to be attained by the individual memory word bits, and effective to provide for a simultaneous attainment of the levels, in a seeking-to manner, of the levels at the end of a limited number of pulses. Advantageously, a constant gate voltage value is concurrently applied to the gate terminals of said cells, such that the cell programming time is unrelated to the threshold level sought.

Abstract: A tightening device, particularly for a sports shoe comprising a first mechanism for transmitting movement to a second mechanism, which is operatively connected to at least a first cable element for fastening the sports shoe, the first mechanism being activated by a third mechanism, which is manually operated by the user.

Abstract: A decoupling circuit for decoupling conduction lines from each other, the circuit including at least one pass gate element having conduction terminals connected to the conduction lines and having at least one control terminal. The decoupling circuit includes at least one protection circuit inserted between the control terminal and at least one of the conduction lines, and including at least one protection transistor connected to the control terminal and to the at least one conduction line, and configured to take in a disturbing signal passing through the pass gate element (N1) to properly decouple the conduction lines from each other on the occurrence of a disturbing condition.

Abstract: A method for testing memory cells, and in particular virgin memory cells, in a multilevel memory device having a plurality of memory cells.