Patents by Inventor Marco Ruta
Marco Ruta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11803202Abstract: A voltage regulator receives an input voltage and produces a regulated output voltage. A first feedback network compares a feedback signal to a reference signal to assert/de-assert a first pulsed control signal when the reference signal is higher/lower than the feedback signal. A second feedback network compares the output voltage to a threshold signal to assert/de-assert a second control signal when the threshold signal is higher/lower than the output voltage. A charge pump is enabled if the second control signal is de-asserted and is clocked by the first pulsed control signal to produce a supply voltage higher than the input voltage. A first pass element is enabled when the second control signal is asserted and is selectively activated when the first pulsed control signal is asserted. A second pass element is selectively activated when the second control signal is de-asserted.Type: GrantFiled: September 21, 2022Date of Patent: October 31, 2023Assignee: STMICROELECTRONICS S.R.L.Inventors: Marco Ruta, Antonio Conte, Michelangelo Pisasale, Agatino Massimo Maccarrone, Francesco Tomaiuolo
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Publication number: 20230336176Abstract: A level-shifter circuit receives one or more input signals in an input level domain and includes provides at an output node an output signal in an output level domain shifted with respect to the input level domain. The circuit includes output circuitry including a first drive node and a second drive node that receive first and second logical signals so that the output signal has a first output level or a second output level in the output level domain as a function of at least one of the first and second logical signals. The circuit includes first and second shift capacitors coupled to the first and second drive nodes as well as capacitor refresh circuitry.Type: ApplicationFiled: April 5, 2023Publication date: October 19, 2023Applicants: STMICROELECTRONICS S.r.l., STMICROELECTRONICS (ALPS) SASInventors: Antonino CONTE, Marco RUTA, Michelangelo PISASALE, Thomas JOUANNEAU
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Publication number: 20230333583Abstract: A LDO regulator circuit comprises an input comparator and driver circuitry including transistors having a current flow path therethrough coupled to an output node of the regulator. First and second driver each comprises: driver transistors having the current flow paths therethrough coupled to the output node, capacitive boost circuitry that applies to the drive transistors a voltage-pumped replica of the comparison signal. Voltage refresh transistor circuitry coupled to the capacitive boost circuitry transfer thereon the voltage-pumped replica.Type: ApplicationFiled: April 4, 2023Publication date: October 19, 2023Applicant: STMICROELECTRONICS S.r.l.Inventors: Antonino CONTE, Marco RUTA, Francesco TOMAIUOLO, Michelangelo PISASALE, Marion Helne GRIMAL
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Publication number: 20230283271Abstract: A system a ring oscillator configured to produce a set of clock signals having the same clock period and a mutual time delay between respective clock signal edges. Comparator circuits are coupled to first and second input nodes and produce a set of comparison signals according to a respective sequence of comparison phases. A set of synchronization circuits is coupled to the ring oscillator and to the plurality of comparator circuits. The synchronization circuits allot, to each one of the comparator circuits, respective time windows for communication over respective communication lines of the comparison signals. The respective time windows are synchronized based on the clock signals. A multiplexer couples the respective communication lines to an output line to sequentially enable each of the comparator circuits to sequentially output respective comparison signals over the output line for the respective time windows thereby forming a composite comparison signal evolving over time.Type: ApplicationFiled: January 23, 2023Publication date: September 7, 2023Inventors: Antonino Conte, Marco Ruta, Michelangelo Pisasale, Agatino Massimo Maccarrone, Francesco Tomaiuolo
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Publication number: 20230170914Abstract: In accordance with an embodiment, a digital-to-analog converter (DAC) includes: a W-2W current mirror that includes a first plurality of MOS transistors having a first width, and second plurality of MOS transistors having a second width that is twice the first width, where ones of the second plurality of MOS transistors are coupled between drains of adjacent ones of the first plurality of MOS transistors; and a bulk bias generator having a plurality of output nodes coupled to corresponding bulk nodes of the first plurality of MOS transistors, wherein the plurality of output nodes are configured to provide voltages that are inversely proportional to temperature.Type: ApplicationFiled: November 10, 2022Publication date: June 1, 2023Inventors: Agatino Massimo Maccarrone, Antonino Conte, Francesco Tomaiuolo, Michelangelo Pisasale, Marco Ruta
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Patent number: 11641191Abstract: In an embodiment a ring oscillator circuit includes a chain of cascade-coupled inverter stages coupled between an oscillator supply voltage node and a reference voltage node, the oscillator supply voltage node configured to provide an oscillator supply voltage, a current generator circuit coupled between the oscillator supply voltage node and a system supply voltage node configured to provide a system supply voltage, the current generator circuit being configured to inject a current into the oscillator supply voltage node and a biasing circuit including a first bias control transistor and a second bias control transistor coupled in series between the reference voltage node and the oscillator supply voltage node, wherein the first bias control transistor is configured to selectively couple the reference voltage node and the oscillator supply voltage node in response to the oscillator control signal being indicative that the ring oscillator circuit is in an inactive operation state.Type: GrantFiled: June 2, 2022Date of Patent: May 2, 2023Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS (ALPS) SASInventors: Antonino Conte, Marco Ruta, Michelangelo Pisasale, Thomas Jouanneau
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Publication number: 20230130268Abstract: A voltage regulator receives an input voltage and produces a regulated output voltage. A first feedback network compares a feedback signal to a reference signal to assert/de-assert a first pulsed control signal when the reference signal is higher/lower than the feedback signal. A second feedback network compares the output voltage to a threshold signal to assert/de-assert a second control signal when the threshold signal is higher/lower than the output voltage. A charge pump is enabled if the second control signal is de-asserted and is clocked by the first pulsed control signal to produce a supply voltage higher than the input voltage. A first pass element is enabled when the second control signal is asserted and is selectively activated when the first pulsed control signal is asserted. A second pass element is selectively activated when the second control signal is de-asserted.Type: ApplicationFiled: September 21, 2022Publication date: April 27, 2023Inventors: Marco Ruta, Antonino Conte, Michelangelo Pisasale, Agatino Massimo Maccarrone, Francesco Tomaiuolo
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Patent number: 11586540Abstract: Apparatuses, systems, and methods to perform continuous read operations are described. A system configured to perform such continuous read operations enables improved access to and processing of data for performance of associated functions. For instance, one apparatus described herein includes a memory device having an array that includes a plurality of pages of memory cells. The memory device includes a page buffer coupled to the array and a continuous read buffer. The continuous read buffer includes a first cache to receive a first segment of data values and a second cache to receive a second segment of the data values from the page buffer. The memory device is configured to perform a continuous read operation on the first and second segments of data from the first cache and the second cache of the continuous read buffer.Type: GrantFiled: August 10, 2021Date of Patent: February 21, 2023Assignee: Micron Technology, Inc.Inventors: Antonino Mondello, Francesco Tomaiuolo, Salvatore Giove, Pierluca Guarino, Fabio Indelicato, Marco Ruta, Maria Luisa Gambina, Giovanni Nunzio Maria Avenia, Carmela Maria Calafato
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Publication number: 20230021601Abstract: In an embodiment a circuit includes a plurality of memory cells, wherein each memory cell includes a phase-change memory storage element coupled in series with a respective current-modulating transistor between a supply voltage node and a reference voltage node, the current-modulating transistors being configured to receive a drive signal at a control terminal and to inject respective programming currents into the respective phase-change memory storage element as a function of the drive signal, a driver circuit configured to produce the drive signal at a common control node, wherein the common control node is coupled to the control terminals of the current-modulating transistors, the drive signal modulating the programming currents to produce SET programming current pulses and RESET programming current pulses and at least one current generator circuit configured to inject a compensation current into the common control node in response to the current-modulating transistors injecting the programming currents inType: ApplicationFiled: July 22, 2022Publication date: January 26, 2023Inventors: Agatino Massimo Maccarrone, Antonino Conte, Francesco Tomaiuolo, Michelangelo Pisasale, Marco Ruta
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Publication number: 20220399880Abstract: In an embodiment a ring oscillator circuit includes a chain of cascade-coupled inverter stages coupled between an oscillator supply voltage node and a reference voltage node, the oscillator supply voltage node configured to provide an oscillator supply voltage, a current generator circuit coupled between the oscillator supply voltage node and a system supply voltage node configured to provide a system supply voltage, the current generator circuit being configured to inject a current into the oscillator supply voltage node and a biasing circuit including a first bias control transistor and a second bias control transistor coupled in series between the reference voltage node and the oscillator supply voltage node, wherein the first bias control transistor is configured to selectively couple the reference voltage node and the oscillator supply voltage node in response to the oscillator control signal being indicative that the ring oscillator circuit is in an inactive operation state.Type: ApplicationFiled: June 2, 2022Publication date: December 15, 2022Inventors: Antonino Conte, Marco Ruta, Michelangelo Pisasale, Thomas Jouanneau
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Publication number: 20210365375Abstract: Apparatuses, systems, and methods to perform continuous read operations are described. A system configured to perform such continuous read operations enables improved access to and processing of data for performance of associated functions. For instance, one apparatus described herein includes a memory device having an array that includes a plurality of pages of memory cells. The memory device includes a page buffer coupled to the array and a continuous read buffer. The continuous read buffer includes a first cache to receive a first segment of data values and a second cache to receive a second segment of the data values from the page buffer. The memory device is configured to perform a continuous read operation on the first and second segments of data from the first cache and the second cache of the continuous read buffer.Type: ApplicationFiled: August 10, 2021Publication date: November 25, 2021Inventors: Antonino Mondello, Francesco Tomaiuolo, Salvatore Giove, Pierluca Guarino, Fabio Indelicato, Marco Ruta, Maria Luisa Gambina, Giovanni Nunzio Maria Avenia, Carmela Maria Calafato
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Patent number: 11093392Abstract: Apparatuses, systems, and methods to perform continuous read operations are described. A system configured to perform such continuous read operations enables improved access to and processing of data for performance of associated functions. For instance, one apparatus described herein includes a memory device having an array that includes a plurality of pages of memory cells. The memory device includes a page buffer coupled to the array and a continuous read buffer. The continuous read buffer includes a first cache to receive a first segment of data values and a second cache to receive a second segment of the data values from the page buffer. The memory device is configured to perform a continuous read operation on the first and second segments of data from the first cache and the second cache of the continuous read buffer.Type: GrantFiled: April 9, 2020Date of Patent: August 17, 2021Assignee: Micron Technology, Inc.Inventors: Antonino Mondello, Francesco Tomaiuolo, Salvatore Giove, Pierluca Guarino, Fabio Indelicato, Marco Ruta, Maria Luisa Gambina, Giovanni Nunzio Maria Avenia, Carmela Maria Calafato
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Publication number: 20200242033Abstract: Apparatuses, systems, and methods to perform continuous read operations are described. A system configured to perform such continuous read operations enables improved access to and processing of data for performance of associated functions. For instance, one apparatus described herein includes a memory device having an array that includes a plurality of pages of memory cells. The memory device includes a page buffer coupled to the array and a continuous read buffer. The continuous read buffer includes a first cache to receive a first segment of data values and a second cache to receive a second segment of the data values from the page buffer. The memory device is configured to perform a continuous read operation on the first and second segments of data from the first cache and the second cache of the continuous read buffer.Type: ApplicationFiled: April 9, 2020Publication date: July 30, 2020Inventors: Antonino Mondello, Francesco Tomaiuolo, Salvatore Giove, Pierluca Guarino, Fabio Indelicato, Marco Ruta, Maria Luisa Gambina, Giovanni Nunzio Maria Avenia, Carmela Maria Calafato
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Patent number: 10621091Abstract: Apparatuses, systems, and methods to perform continuous read operations are described. A system configured to perform such continuous read operations enables improved access to and processing of data for performance of associated functions. For instance, one apparatus described herein includes a memory device having an array that includes a plurality of pages of memory cells. The memory device includes a page buffer coupled to the array and a continuous read buffer. The continuous read buffer includes a first cache to receive a first segment of data values and a second cache to receive a second segment of the data values from the page buffer. The memory device is configured to perform a continuous read operation on the first and second segments of data from the first cache and the second cache of the continuous read buffer.Type: GrantFiled: May 4, 2018Date of Patent: April 14, 2020Assignee: Micron Technology, Inc.Inventors: Antonino Mondello, Francesco Tomaiuolo, Salvatore Giove, Pierluca Guarino, Fabio Indelicato, Marco Ruta, Maria Luisa Gambina, Giovanni Nunzio Maria Avenia, Carmela Maria Calafato
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Publication number: 20190340125Abstract: Apparatuses, systems, and methods to perform continuous read operations are described. A system configured to perform such continuous read operations enables improved access to and processing of data for performance of associated functions. For instance, one apparatus described herein includes a memory device having an array that includes a plurality of pages of memory cells. The memory device includes a page buffer coupled to the array and a continuous read buffer. The continuous read buffer includes a first cache to receive a first segment of data values and a second cache to receive a second segment of the data values from the page buffer. The memory device is configured to perform a continuous read operation on the first and second segments of data from the first cache and the second cache of the continuous read buffer.Type: ApplicationFiled: May 4, 2018Publication date: November 7, 2019Inventors: Antonino Mondello, Francesco Tomaiuolo, Salvatore Giove, Pierluca Guarino, Fabio Indelicato, Marco Ruta, Maria Luisa Gambina, Giovanni Nunzio Maria Avenia, Carmela Maria Calafato