Abstract: An integrated circuit for use in remote keyless entry (RKE) applications is disclosed that integrates two drivers with a shared dual mode antenna. The drivers may be integrated on a single integrated circuit chip using high voltage (HV) complementary metal-oxide-semiconductor (CMOS) processes. In immobilizer mode of operation, an immobilizer driver coupled to the dual mode antenna is configured to drive the dual mode antenna, while an LF mode driver coupled to the dual mode antenna is configured to be idle. In LF mode of operation, the LF mode driver is configured to drive the dual mode antenna, while the immobilizer driver is configured to be idle. In some implementations, the drivers are coupled to a common node coupled to the dual mode antenna and are selectively biased with different supply voltages based on the current mode of operation to prevent current leakage and component damage.

Abstract: A carrier compensation reader compensates a carrier signal. The carrier compensation reader transmits, via an antenna, a first carrier signal and obtains a second carrier signal based on the first carrier signal. The carrier compensation reader configures a compensation circuit to receive a receiver output signal based on the second carrier signal and generate a compensation signal based on the receiver output signal to compensate the second carrier signal. The carrier compensation reader obtains a carrier compensation signal summing the second carrier signal and the compensation signal.

Abstract: In certain embodiments, a circuit for image frequency rejection includes an analog adder-amplifier that has a transistor pair. The adder-amplifier is configured to receive a plurality of downmixed or upmixed in-phase and quadrature-phase signals, and to add an in-phase signal and a quadrature-phase signal applied at control inputs of both transistors of the transistor pair. Both transistors of the transistor pair are connectable to a same load resistor for addition of the in-phase signal and the quadrature-phase signal applied at the control inputs of both transistors. The adder-amplifier is configured to output, based on adding the in-phase signal and the quadrature-phase signal applied at the control inputs of both transistors of the transistor pair, one or more summed signals.

Abstract: A carrier compensation reader compensates a carrier signal. The carrier compensation reader transmits, via an antenna, a first carrier signal and obtains a second carrier signal based on the first carrier signal. The carrier compensation reader configures a compensation circuit to receive a receiver output signal based on the second carrier signal and generate a compensation signal based on the receiver output signal to compensate the second carrier signal. The carrier compensation reader obtains a carrier compensation signal summing the second carrier signal and the compensation signal.

Abstract: An integrated circuit for use in remote keyless entry (RKE) applications is disclosed that integrates two drivers with a shared dual mode antenna. The drivers may be integrated on a single integrated circuit chip using high voltage (HV) complementary metal-oxide-semiconductor (CMOS) processes. In immobilizer mode of operation, an immobilizer driver coupled to the dual mode antenna is configured to drive the dual mode antenna, while an LF mode driver coupled to the dual mode antenna is configured to be idle. In LF mode of operation, the LF mode driver is configured to drive the dual mode antenna, while the immobilizer driver is configured to be idle. In some implementations, the drivers are coupled to a common node coupled to the dual mode antenna and are selectively biased with different supply voltages based on the current mode of operation to prevent current leakage and component damage.

Abstract: A receiver, receiving method, and use of an in-phase signal and a quadrature-phase signal is provided, that includes a mixer in the receiving path, an oscillator whose output is connected to a mixer input of the mixer, whereby the oscillator is formed to output a base signal, oscillating at a base frequency, at the output, a clock generation device to generate a clock signal from the base signal, whose input is connected to the output of the oscillator, whereby the clock generation device has a frequency converter for converting a base frequency of the base signal by the factor F=x+A, where x is a positive whole number and A a rational number between 0 and 1, and a signal processing device, which is connected downstream of the mixer in the receive path, whereby the signal processing device is connected to the clock generation device for control with the clock signal.

Abstract: A circuit and method for image frequency rejection is provided that includes an analog dual-quadrature mixer device whose signal inputs for an in-phase-signal and a quadrature-phase signal are connected to an input circuit in the signal path and whose oscillator inputs for an in-phase oscillator signal and a quadrature-phase oscillator signal are connected to a local oscillator device, having an analog adder-amplifier device, which has a number of transistor pairs, in which in each case both transistors of each transistor pair are connected to the same load resistor for the addition of the signals applied at the control inputs of both transistors, and in which the control inputs of both transistors are connected downstream of the outputs of analog dual-quadrature mixer device, and having a multistage analog polyphase filter whose inputs are connected to outputs of the adder-amplifier device.

Abstract: A circuit and method for image frequency rejection is provided that includes an analog dual-quadrature mixer device whose signal inputs for an in-phase-signal and a quadrature-phase signal are connected to an input circuit in the signal path and whose oscillator inputs for an in-phase oscillator signal and a quadrature-phase oscillator signal are connected to a local oscillator device, having an analog adder-amplifier device, which has a number of transistor pairs, in which in each case both transistors of each transistor pair are connected to the same load resistor for the addition of the signals applied at the control inputs of both transistors, and in which the control inputs of both transistors are connected downstream of the outputs of analog dual-quadrature mixer device, and having a multistage analog polyphase filter whose inputs are connected to outputs of the adder-amplifier device.

Abstract: A circuit for a loop antenna having a first antenna terminal and a second antenna terminal with an antenna impedance, and method for tuning an overall impedance that has an antenna impedance of a loop antenna and a tuning impedance, with an output amplifier for amplifying a transmit signal that has an output for connection to the first antenna terminal of the loop antenna, with a tuning device designed for automatic tuning that has a terminal, which is separated from the output of the output amplifier for connection to the second antenna terminal, in which the tuning device has an adjustable tuning impedance that is connected to the terminal, in which the tuning device has a measurement device that is connected to the tuning impedance in order to measure a voltage amplitude across the tuning impedance, in which the tuning device has a computing unit that is connected to the measurement device and the adjustable tuning impedance, and in which the computing unit is designed for automatic adjustment of the tunin

Abstract: A signal processing device and signal processing method is provided that includes a detection unit for detecting a signal strength of a signal, whereby the detection unit is configured to output a detection value that represents the signal strength of the signal; a settable digital filter connected upstream of the detection unit, whereby filter coefficients for setting a transfer characteristic of the filter are assigned to an amplification or attenuation of the signal by the filter; a digital multiplication unit, which is connected upstream of the detection unit for amplification or attenuation of the signal, whereby the multiplication unit is configured to compensate partially for the amplification or attenuation of the filter, whereby the compensation is encumbered with a residual error; and a correction unit to apply to the detection value a correction value at least partially compensating for the residual error.

Abstract: A circuit and method for image frequency rejection is provided that includes an analog dual-quadrature mixer device whose signal inputs for an in-phase-signal and a quadrature-phase signal are connected to an input circuit in the signal path and whose oscillator inputs for an in-phase oscillator signal and a quadrature-phase oscillator signal are connected to a local oscillator device, having an analog adder-amplifier device, which has a number of transistor pairs, in which in each case both transistors of each transistor pair are connected to the same load resistor for the addition of the signals applied at the control inputs of both transistors, and in which the control inputs of both transistors are connected downstream of the outputs of analog dual-quadrature mixer device, and having a multistage analog polyphase filter whose inputs are connected to outputs of the adder-amplifier device.

Abstract: A circuit for a loop antenna having a first antenna terminal and a second antenna terminal with an antenna impedance, and method for tuning an overall impedance that has an antenna impedance of a loop antenna and a tuning impedance, with an output amplifier for amplifying a transmit signal that has an output for connection to the first antenna terminal of the loop antenna, with a tuning device designed for automatic tuning that has a terminal, which is separated from the output of the output amplifier for connection to the second antenna terminal, in which the tuning device has an adjustable tuning impedance that is connected to the terminal, in which the tuning device has a measurement device that is connected to the tuning impedance in order to measure a voltage amplitude across the tuning impedance, in which the tuning device has a computing unit that is connected to the measurement device and the adjustable tuning impedance, and in which the computing unit is designed for automatic adjustment of the tunin

Abstract: A transducer device for converting an analog DC voltage signal into a digital signal is provided, with an oscillator device for outputting a first oscillator signal and a second oscillator signal, whereby the oscillator device is formed to generate the first oscillator signal and the second oscillator signal phase-locked to one another and with the substantially same frequency from a reference signal, with an analog frequency converter connected to the oscillator device for transforming the analog DC voltage signal by the first oscillator signal in a first spectral range with a first center frequency to obtain a transformed signal, with an analog-to-digital converter for converting the transformed signal into a transformed digital signal; and with a digital frequency converter connected to the oscillator device for transforming the transformed digital signal by means of the second oscillator signal in a second spectral range with a second center frequency to obtain the digital signal.

Abstract: A receiver, receiving method, and use of an in-phase signal and a quadrature-phase signal is provided, that includes a mixer in the receiving path, an oscillator whose output is connected to a mixer input of the mixer, whereby the oscillator is formed to output a base signal, oscillating at a base frequency, at the output, a clock generation device to generate a clock signal from the base signal, whose input is connected to the output of the oscillator, whereby the clock generation device has a frequency converter for converting a base frequency of the base signal by the factor F=x+A, where x is a positive whole number and A a rational number between 0 and 1, and a signal processing device, which is connected downstream of the mixer in the receive path, whereby the signal processing device is connected to the clock generation device for control with the clock signal.

Abstract: A signal processing device and signal processing method is provided that includes a detection unit for detecting a signal strength of a signal, whereby the detection unit is configured to output a detection value that represents the signal strength of the signal; a settable digital filter connected upstream of the detection unit, whereby filter coefficients for setting a transfer characteristic of the filter are assigned to an amplification or attenuation of the signal by the filter; a digital multiplication unit, which is connected upstream of the detection unit for amplification or attenuation of the signal, whereby the multiplication unit is configured to compensate partially for the amplification or attenuation of the filter, whereby the compensation is encumbered with a residual error; and a correction unit to apply to the detection value a correction value at least partially compensating for the residual error.

Abstract: A transducer device for converting an analog DC voltage signal into a digital signal is provided, with an oscillator device for outputting a first oscillator signal and a second oscillator signal, whereby the oscillator device is formed to generate the first oscillator signal and the second oscillator signal phase-locked to one another and with the substantially same frequency from a reference signal, with an analog frequency converter connected to the oscillator device for transforming the analog DC voltage signal by the first oscillator signal in a first spectral range with a first center frequency to obtain a transformed signal, with an analog-to-digital converter for converting the transformed signal into a transformed digital signal; and with a digital frequency converter connected to the oscillator device for transforming the transformed digital signal by means of the second oscillator signal in a second spectral range with a second center frequency to obtain the digital signal.

Abstract: An integrated amplifier circuit is provided with an amplifier that is composed of at least two amplifier regions, the amplifier regions being arranged about a symmetry point, wherein each amplifier region has a plurality of transistors in a transistor region, and wherein transistors from different amplifier areas are arranged within the same transistor region. According to an aspect, provision is made that each amplifier region has at least two transistors.

Abstract: In a PLL circuit including a voltage-controlled oscillator, a phase detector and a final control element, the final control element contains two separate channels, between the phase detector and the voltage controlled oscillator, wherein one channel processes the useful signal components and the other channel processes the disturbance signal components of the synchronization pulses. Each channel has two tracks, for generation of a potential difference, wherein each track is connected to a capacitor plate.

Abstract: In a bi-directional contactless data transmission, a procedure aims to prevent the communication distance from being extended by unauthorized persons using radio repeaters. The procedure involves establishing a fixed relationship of a selected physical parameter of an electromagnetic signal. For example, the frequency of the signal received by a transponder is multiplied with a number to provide a different frequency, and a response signal having this different frequency is transmitted back to a base unit. In the base unit, the received frequency of this response signal is divided by the same number and the result is compared to the frequency of the originally emitted signal. If the resulting difference is below a preset threshold, then there is a fixed frequency relationship between the two signals, the process concludes that there has been no unauthorized extension of the communication distance by using repeaters, and the further authentication is carried out.

Abstract: In a PLL circuit comprising a voltage-controlled oscillator, a phase detector and a final control element, the final control element contains two separate channels, between the phase detector and the voltage controlled oscillator, one channel processing the useful signal components and the other channel processing the disturbance signal components of the synchronisation pulses. Each channel has two tracks, for generation of a potential difference, each track being connected to a capacitor plate.