Abstract: A semiconductor package includes a power semiconductor chip having a control electrode, a first load electrode and a second load electrode. The package also includes a first terminal conductor electrically coupled to the control electrode, a second terminal conductor electrically coupled to the first load electrode and a third terminal conductor electrically coupled to the second load electrode. Further, the package includes a temperature sensor electrically coupled to at least two of the first, second and third terminal conductor.

Abstract: A chip arrangement is provided, the chip arrangement, including: a carrier; at least one chip including at least one contact pad disposed over the carrier; an encapsulation material at least partially surrounding the at least one chip and the carrier; and at least one low temperature co-fired ceramic sheet disposed over a side of the carrier.

Abstract: A chip arrangement is provided, the chip arrangement, including: a carrier; at least one chip including at least one contact pad disposed over the carrier; an encapsulation material at least partially surrounding the at least one chip and the carrier; and at least one low temperature co-fired ceramic sheet disposed over a side of the carrier.

Abstract: A semiconductor package includes a power semiconductor chip having a control electrode, a first load electrode and a second load electrode. The package also includes a first terminal conductor electrically coupled to the control electrode, a second terminal conductor electrically coupled to the first load electrode and a third terminal conductor electrically coupled to the second load electrode. Further, the package includes a temperature sensor electrically coupled to at least two of the first, second and third terminal conductor.

Abstract: An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads.

Abstract: A semiconductor device includes at least one first semiconductor element and two interconnectors for electrically coupling the at least one first semiconductor element to external. A spacing between the two interconnectors corresponds to a size of a second semiconductor element. The second semiconductor element can be affixed between the two interconnectors.

Abstract: An embodiment of the invention relates to an apparatus including a magnetic device and a related method. A multilayer substrate is constructed with a winding formed in a metallic layer, an electrically insulating layer above the metallic layer, and a via formed in the electrically insulating layer to couple the winding to a circuit element positioned on the multilayer substrate. A depression is formed in the multilayer substrate, and a polymer solution, preferably an epoxy, containing a ferromagnetic component such as nanocrystaline nickel zinc ferrite is deposited within a mold positioned on a surface of the multilayer substrate above the winding and in the depression. An integrated circuit electrically coupled to the winding may be located on the multilayer substrate. The multilayer substrate may be a semiconductor substrate or a printed wiring board, and the circuit element may be an integrated circuit formed on the multilayer substrate.

Abstract: A chip arrangement is provided: the chip arrangement including: a carrier; a chip disposed over the carrier; a ceramic layer formed over the chip and on at least a portion of the carrier; wherein the chip is surrounded by the carrier and the ceramic layer.

Abstract: An embodiment of the invention relates to an apparatus including a magnetic device and a related method. A multilayer substrate is constructed with a winding formed in a metallic layer, an electrically insulating layer above the metallic layer, and a via formed in the electrically insulating layer to couple the winding to a circuit element positioned on the multilayer substrate. A depression is formed in the multilayer substrate, and a polymer solution, preferably an epoxy, containing a ferromagnetic component such as nanocrystaline nickel zinc ferrite is deposited within a mold positioned on a surface of the multilayer substrate above the winding and in the depression. An integrated circuit electrically coupled to the winding may be located on the multilayer substrate. The multilayer substrate may be a semiconductor substrate or a printed wiring board, and the circuit element may be an integrated circuit formed on the multilayer substrate.

Abstract: An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads.

Abstract: An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads.

Abstract: One example of the invention relates to a circuit arrangement for actuating a high-side transistor which includes a control terminal and a load terminal. The circuit arrangement includes a driver circuit that is designed to generate, in response to a control signal, a driver signal for the control terminal of the high-side transistor. A supply circuit is capacitively coupled to a radio-frequency signal source and is designed to provide a supply voltage to the driver circuit, the supply voltage being referenced to a floating reference potential.

Abstract: One example of the invention relates to a circuit arrangement for actuating a high-side transistor which includes a control terminal and a load terminal. The circuit arrangement includes a driver circuit that is designed to generate, in response to a control signal, a driver signal for the control terminal of the high-side transistor. A supply circuit is capacitively coupled to a radio-frequency signal source and is designed to provide a supply voltage to the driver circuit, the supply voltage being referenced to a floating reference potential.

Abstract: An embodiment of the invention relates to an apparatus including a magnetic device and a related method. A multilayer substrate is constructed with a winding formed in a metallic layer, an electrically insulating layer above the metallic layer, and a via formed in the electrically insulating layer to couple the winding to a circuit element positioned on the multilayer substrate. A depression is formed in the multilayer substrate, and a polymer solution, preferably an epoxy, containing a ferromagnetic component such as nanocrystaline nickel zinc ferrite is deposited within a mold positioned on a surface of the multilayer substrate above the winding and in the depression. An integrated circuit electrically coupled to the winding may be located on the multilayer substrate. The multilayer substrate may be a semiconductor substrate or a printed wiring board, and the circuit element may be an integrated circuit formed on the multilayer substrate.

Abstract: An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads.

Abstract: In an electronic ballast the output d.c. voltage (U) of a PFC intermediate circuit (3) is to be regulated. The intermediate circuit (3) has a clocked switch (S) which is controlled by a regulation circuit (7). The regulation circuit (7) includes two counters (Z1, Z2). The counter (Z1) has a greater number of count stages than the counter (Z2). The counter (Z1) is counted upwards or downwards in dependence upon the regulation difference. The counter (Z2) is repeatedly counted only in one direction and for example reset by a reset signal. By comparing the counts of corresponding count stages of the two counters (Z1) and (Z2) in a comparator, the switch on time (ton) for the clock switch (S) is determined.

Abstract: In an operating circuit for a gas discharge lamp 1, in particular in the aeronautical field, an inductance L1 is connected upstream of the gas discharge lamp 1 and a switch V3 periodically controlled by an electronic control system 3 controls the current through the inductance L1. In order also to be able to achieve very low dimming values with freedom from flicker, by virtue of the switch V3 being switched into a conducting condition by means of the electronic control system 3 a constant dc voltage Uin is applied to the inductance L1 for a constant switch-on duration ton. By the switch V3 being switched off at the end of the switch-on duration ton the energy stored by the inductance L1 is discharged to the gas discharge lamp 1. In each case after discharge of the inductance L1 the electronic control system 3 closes the switch V3 periodically again for the switch-on duration ton.

Abstract: In an electronic ballast the output d.c. voltage (U) of a PFC intermediate circuit (3) is to be regulated. The intermediate circuit (3) has a clocked switch (S) which is controlled by a regulation circuit (7). The regulation circuit (7) includes two counters (Z1, Z2). The counter (Z1) has a greater number of count stages than the counter (Z2). The counter (Z1) is counted upwards or downwards in dependence upon the regulation difference. The counter (Z2) is repeatedly counted only in one direction and for example reset by means of a reset signal. By means of comparison the counts of corresponding count stages of the two counters (Z1) and (Z2) in a comparator, the switch on time (ton) for the clock switch (S) is determined.