Abstract: A package is disclosed. In one example, the package comprises a carrier, a first chip with an integrated transistor and comprising a first terminal attached on the carrier, a second terminal, and a third terminal, wherein the first terminal and the third terminal are formed on one main surface of the first chip and the second terminal is formed on an opposing other main surface of the first chip. A conductive structure is attached on the second terminal, an encapsulant is at least partially encapsulating the carrier, the first chip, and the conductive structure, and an insulating layer is arranged on a surface portion of the conductive structure or of the carrier. The surface portion is exposed beyond the encapsulant.

Abstract: A package includes a carrier, an electronic component on the carrier, an encapsulant encapsulating at least part of the carrier and the electronic component, and at least one lead extending beyond the encapsulant and having a punched surface, wherein at least part of at least one side flank of the encapsulant has a sawn texture.

Abstract: A package includes a single integral electrically conductive body, a first chip with an integrated transistor and including a first terminal, a second terminal, and a third terminal, wherein the second terminal and the third terminal are formed on one main surface of the first chip and the first terminal is formed on an opposing main surface of the first chip, and a second chip with an integrated transistor and comprising a fourth, fifth and sixth terminals, wherein the fourth terminal and the sixth terminal are formed on one main surface of the second chip and the fifth terminal is formed on another surface of the second chip, wherein the first chip and the second chip are connected to form a half bridge.

Abstract: A semiconductor package includes: a leadframe having a die carrier and at least one first lead connected with the die carrier; a semiconductor transistor die connected with the die carrier and having a first surface and a second surface opposite to the first surface, a source pad disposed on the first surface, and a drain pad disposed on the second surface, the first surface facing a bottom side of the semiconductor package and the second surface facing a top side of the package; and a clip. The source pad is connected with the clip by at least one electrical connector.

Abstract: A power semiconductor package comprises a leadframe comprising a first die pad, a second die pad and a plurality of external contacts. The first and second die pads are separated by a first gap. A power semiconductor die is arranged on and electrically coupled to a first side of the first die pad. A diode is arranged on and electrically coupled to a first side of the second die pad. A molded body encapsulates the power semiconductor die and the diode, the molded body having a first side, an opposite second side and lateral sides connecting the first and second sides. A second side of the first die pad is exposed from the second side of the molded body. A second side of the second die pad is completely covered by an electrically insulating material.

Abstract: A semiconductor package is disclosed. In one example, the semiconductor package comprises a package body and a second die pad at least partially encapsulated in the package body. A first semiconductor die is at least partially encapsulated in the package body and arranged on the first die pad. A further device at least partially encapsulated in the package body and arranged on the second die pad. At least one first lead is connected with the first contact pad of the first semiconductor die. At least one second lead is connected with the second contact pad of the further device. An electrical conductor is connected between the at least one first lead and the at least one second lead, the electrical conductor being completely encapsulated in the package body.

Abstract: A transistor package includes a semiconductor transistor chip having opposite first and second surfaces, one or a plurality of first load electrodes, one or a plurality of second load electrodes, and a control electrode on the first surface. A leadframe faces the first surface of the semiconductor transistor chip and includes a first terminal, a second terminal, and a control terminal of the package which are exposed at a bottom of the package. The first terminal is electrically coupled to the first load electrode(s). The second terminal is electrically coupled to the second load electrode(s). The control terminal is electrically coupled to the control electrode. The first terminal is aligned with a first side of the package. The second terminal is aligned with a second side opposite the first side. The control terminal is aligned with a third side of the package which connects between the first and second sides.