Abstract: An integrated circuit includes a first memory, a second memory, a processor, and a descrambler. The first memory is configured to store a key. The first memory is a one-time-programmable memory. The processor is configured to: determine whether the first memory has been programmed; and in response to the first memory not having been programmed, (i) load firmware from a third memory into the second memory, and (ii) execute the firmware. The third memory is separate from the integrated circuit. The processor is also configured to, in response to the first memory having been programmed, load the firmware from the third memory into the second memory. The descrambler is configured to, in response to the first memory having been programmed, descramble the firmware based on the key.

Abstract: A system-on-a-chip including a first one-time-programmable memory, a second memory, a test interface, an input circuit, and a processor. The input circuit is configured to receive data transmitted from a third memory to the system-on-a-chip. The processor is configured to, while booting up the system-on-a-chip, determine whether a first one-time-programmable memory has been previously programmed. The processor is also configured to (i) in response to the first one-time-programmable memory not having been previously programmed, enable the test interface for debugging of the system-on-a-chip, (ii) based on the first one-time-programmable memory having been previously programmed, disable the test interface, and (iii) subsequent to one of the enabling of the test interface and the disabling of the test interface, load the data from the third memory into the second memory.

Abstract: A system-on-a-chip includes a first memory and a processor. The first memory is configured to store a boot code. The processor is configured to (i) access the first memory, and (ii) execute the boot code when booting up. The processor is configured to, while booting up, determine whether a first one-time-programmable memory has been previously programmed based on the boot code. The processor is configured to, in response to the first one-time-programmable memory not having been previously programmed based on the boot code, (i) load firmware from a second memory into a third memory, and (ii) execute the firmware loaded into the third memory. The processor is configured to, in response to the first one-time-programmable memory having been previously programmed, verify a digital signature of the firmware.

Abstract: Apparatus having corresponding methods and computer programs comprise: a processor; a test interface that is in communication with the processor only when the test interface is enabled; a first one-time-programmable (OTP) memory; and a non-volatile memory to store boot code for the processor, wherein when the processor is booted, the boot code causes the processor to test the first OTP memory; wherein the boot code causes the processor to enable the test interface when the first OTP memory has not been programmed; and wherein the boot code causes the processor to disable the test interface when the first OTP memory has been programmed.