Abstract: A disk drive comprising a rotatable disk, a head actuated over the disk, and a controller is disclosed. The controller is configured to write data on the disk using the head, to store logical-to-physical mapping information for data already written on the disk in a circular buffer as the data is written on the disk, and to write a plurality of metadata files on the disk using the head, wherein the plurality of metadata files are interspersed with the data on the disk and each of the metadata files includes contents of the circular buffer at a time the metadata file is written on the disk.

Abstract: A disk drive is disclosed that utilizes an additional address mapping layer between logical addresses used by a host system and physical locations in the disk drive. Physical locations configured to store metadata information can be excluded from the additional address mapping layer. As a result, a reduced size translation table can be maintained by the disk drive. Improved performance, reduced costs, and improved security can thereby be attained.

Abstract: The present invention relates to methods and systems for efficiently accessing data stored on a data storage device. The data storage device may comprise various types of media, such as shingled media and non-shingled media, alone or in combination. The data storage device may employ a logical block address space for specifying location of blocks of data stored on the data storage device. In addition, pre-determined sequential ranges of logical block addresses are grouped together and may be referenced collectively. In some embodiments, each type of media type may be partitioned into sections for containing different sizes of collections. Each collection of logical block addresses may be allocated to an arbitrary logical slot. Each logical slot may then be linked to a physical slot on the data storage device.

Abstract: A disk drive is disclosed comprising a head actuated over a rotatable disk. A write operation is processed to write data on the disk using the head, wherein prior to writing the data on the disk, logical-to-physical mapping information is stored in a circular buffer, wherein the logical-to-physical mapping information identifies locations on the disk to write the data. A plurality of metadata files are written on the disk using the head, wherein the plurality of metadata files are interspersed with the data on the disk and each of the metadata files includes contents of the circular buffer at a time the metadata file is written on the disk. When the write operation is aborted, the logical-to-physical mapping information in the circular buffer is modified to identify the locations on the disk actually written.

Abstract: An integrated circuit includes a first memory, a second memory, a processor, and a descrambler. The first memory is configured to store a key. The first memory is a one-time-programmable memory. The processor is configured to: determine whether the first memory has been programmed; and in response to the first memory not having been programmed, (i) load firmware from a third memory into the second memory, and (ii) execute the firmware. The third memory is separate from the integrated circuit. The processor is also configured to, in response to the first memory having been programmed, load the firmware from the third memory into the second memory. The descrambler is configured to, in response to the first memory having been programmed, descramble the firmware based on the key.

Abstract: A disk drive subsystem is disclosed that implements a process for metadata recovery. Certain embodiments relate to recovery of metadata containing information indicating the physical locations in the disk drive in which host data is stored. In an embodiment, the metadata to be recovered is disposed in sequence with, or in physical association with host data that it describes. Recovery is accomplished by identifying metadata that is valid, but is absent from one or more translation tables containing translation information. Metadata portion can include one or more identifiers that are sequentially related to identifiers included in one or more other metadata portions. Performance improvements can thereby be attained.

Abstract: A system-on-a-chip including a first one-time-programmable memory, a second memory, a test interface, an input circuit, and a processor. The input circuit is configured to receive data transmitted from a third memory to the system-on-a-chip. The processor is configured to, while booting up the system-on-a-chip, determine whether a first one-time-programmable memory has been previously programmed. The processor is also configured to (i) in response to the first one-time-programmable memory not having been previously programmed, enable the test interface for debugging of the system-on-a-chip, (ii) based on the first one-time-programmable memory having been previously programmed, disable the test interface, and (iii) subsequent to one of the enabling of the test interface and the disabling of the test interface, load the data from the third memory into the second memory.

Abstract: A system-on-a-chip includes a first memory and a processor. The first memory is configured to store a boot code. The processor is configured to (i) access the first memory, and (ii) execute the boot code when booting up. The processor is configured to, while booting up, determine whether a first one-time-programmable memory has been previously programmed based on the boot code. The processor is configured to, in response to the first one-time-programmable memory not having been previously programmed based on the boot code, (i) load firmware from a second memory into a third memory, and (ii) execute the firmware loaded into the third memory. The processor is configured to, in response to the first one-time-programmable memory having been previously programmed, verify a digital signature of the firmware.

Abstract: Apparatus having corresponding methods and computer programs comprise: a processor; a test interface that is in communication with the processor only when the test interface is enabled; a first one-time-programmable (OTP) memory; and a non-volatile memory to store boot code for the processor, wherein when the processor is booted, the boot code causes the processor to test the first OTP memory; wherein the boot code causes the processor to enable the test interface when the first OTP memory has not been programmed; and wherein the boot code causes the processor to disable the test interface when the first OTP memory has been programmed.