Abstract: An electronic device as taught herein offers reduced on-chip memory processing of graphics data, while also offering low memory bandwidth requirements. The electronic device includes a host block with off-chip memory, a graphics processing block with on-chip memory, a display controller, and a graphics display. The off-chip memory stores a frame of graphics data. The graphics processing block processes that frame of graphics data in blocks, or “tiles,” of graphics data. For each tile, the graphics processing block fetches rendering instructions and graphics data corresponding to that tile from the off-chip memory, stores the graphics data in the on-chip memory, and renders pixel values for the tile by processing the graphics data in accordance with the rendering instructions. The graphics processing block then sends the rendered pixel values for the tile directly to the display controller and partially updates the graphics display memory with those rendered pixel values.

Abstract: An electronic device as taught herein offers reduced on-chip memory processing of graphics data, while also offering low memory bandwidth requirements. The electronic device includes a host block with off-chip memory, a graphics processing block with on-chip memory, a display controller, and a graphics display. The off-chip memory stores a frame of graphics data. The graphics processing block processes that frame of graphics data in blocks, or “tiles,” of graphics data. For each tile, the graphics processing block fetches rendering instructions and graphics data corresponding to that tile from the off-chip memory, stores the graphics data in the on-chip memory, and renders pixel values for the tile by processing the graphics data in accordance with the rendering instructions. The graphics processing block then sends the rendered pixel values for the tile directly to the display controller and partially updates the graphics display memory with those rendered pixel values.