Abstract: A graphic processor device is implemented on a field programmable gate array (“FPGA”) circuitry comprises a pipeline formatter that sets graphic commands and vertex data into structures, and a rasterizer that interpolates between vertices in the vertex data to generate lines and filling between at least one edge to generate a structure, wherein output of the rasterizer is a stream of fragments that become pixels. The graphic processor device further includes a frame buffer that receives a stream of fragments and blends a plurality of fragments before the plurality of fragments are stored in a frame buffer, and an output processor configured to retrieve a plurality of fragments from the frame buffer and transmits a plurality of pixels according to a predefined resolution.

Abstract: A rasterizer in a graphic processor device implemented on a field programmable gate array circuitry (FPGA). The rasterizer comprises a preprocessor that creates data packets to generate at least one line, a main module that generates a stream of data fragments that become pixels, and a postprocessor that combines the data fragments and pipeline commands into one output to a fragment processor.

Abstract: A graphic processor device is implemented on a field programmable gate array (“FPGA”) circuitry comprises a pipeline formatter that sets graphic commands and vertex data into structures, and a rasterizer that interpolates between vertices in the vertex data to generate lines and filling between at least one edge to generate a structure, wherein output of the rasterizer is a stream of fragments that become pixels. The graphic processor device further includes a frame buffer that receives a stream of fragments and blends a plurality of fragments before the plurality of fragments are stored in a frame buffer, and an output processor configured to retrieve a plurality of fragments from the frame buffer and transmits a plurality of pixels according to a predefined resolution.

Abstract: A rasterizer in a graphic processor device implemented on a field programmable gate array circuitry (FPGA). The rasterizer comprises a preprocessor that creates data packets to generate at least one line, a main module that generates a stream of data fragments that become pixels, and a postprocessor that combines the data fragments and pipeline commands into one output to a fragment processor.