Abstract: A receiver circuit for detecting and waking up to a wakeup impulse sequence is provided. Herein, a transmitter circuit is configured to transmit a wakeup impulse sequence to wake up a receiver circuit. The receiver circuit includes a main receiver circuit and a wakeup receiver circuit. The main receiver circuit, which consumes far more energy than the wakeup receiver circuit, will remain in sleep mode as much as possible to conserve power. While the main receiver circuit is asleep, the wakeup receiver circuit is configured to detect the wakeup impulse sequence and wake up the main receiver circuit if the wakeup impulse sequence is intended for the receiver circuit. By keeping the main receiver circuit asleep as much as possible, it is possible to reduce power consumption, thus making the receiver circuit an ideal receiver option for an Internet-of-Things (IoT) device(s).

Abstract: Group delay determination in a communication circuit is disclosed. The communication circuit includes a power amplifier circuit that amplifies a radio frequency (RF) signal based on a modulated voltage and a power management integrated circuit (PMIC) that generates the modulated voltage. Herein, the PMIC includes a group delay determination circuit to determine a relative group delay between the modulated voltage and a modulated current, which is internal to the power amplifier circuit and unknown to the PMIC, solely based on signals known to the PMIC. The determined relative group delay can help to time align the modulated voltage with the modulated current at the power amplifier circuit to improve error vector magnitude (EVM) and/or adjacent channel leakage ratio (ACLR). Further, by determining the relative group delay based on known signals to the PMIC, it is possible to achieve good time alignment between the modulated voltage and the modulated current.

Abstract: Group delay determination in a communication circuit is disclosed. The communication circuit includes a power amplifier circuit that amplifies a radio frequency (RF) signal based on a modulated voltage and a power management integrated circuit (PMIC) that generates the modulated voltage. Herein, the PMIC includes a group delay determination circuit to determine a relative group delay between the modulated voltage and a modulated current, which is internal to the power amplifier circuit and unknown to the PMIC, solely based on signals known to the PMIC. The determined relative group delay can help to time align the modulated voltage with the modulated current at the power amplifier circuit to improve error vector magnitude (EVM) and/or adjacent channel leakage ratio (ACLR). Further, by determining the relative group delay based on known signals to the PMIC, it is possible to achieve good time alignment between the modulated voltage and the modulated current.

Abstract: An envelope tracking (ET) radio frequency (RF) front-end circuit is provided. The ET RF front-end circuit includes an ET integrated circuit(s) (ETIC(s)), a local transceiver circuit, a target voltage circuit(s), and a number of power amplifiers. The local transceiver circuit receives an input signal(s) from a coupled baseband transceiver and generates a number of RF signals. The target voltage circuit(s) generates a time-variant ET target voltage(s) based on the input signal(s). The ETIC(s) generates multiple ET voltages based on the time-variant ET target voltage(s). The power amplifiers amplify the RF signals based on the ET voltages. Given that the time-variant ET target voltage(s) is generated inside the self-contained ET RF front-end circuit, it is possible to reduce distortion in the time-variant ET target voltage(s), thus helping to improve operating efficiency of the power amplifiers, especially when the RF signals are modulated with a higher modulation bandwidth (e.g., ?200 MHz).

Abstract: A complementary envelope detector contemplates using two pair of mirrored transistors to provide a differential output envelope signal to an associated envelope tracking integrated circuit (ETIC) that supplies control voltages to an array of power amplifiers. While bipolar junction transistors (BJTs) may be used, other exemplary aspects use field effect transistors (FETs). In an exemplary aspect, a first pair are negative channel FETs (nFETs) and a second pair are positive channel FETs (pFETs).

Abstract: An average power tracking (APT) power amplifier apparatus is provided. In a non-limiting example, the APT power amplifier apparatus includes multiple sets of power amplifier circuits configured to amplify a radio frequency (RF) signal(s) for transmission in different polarizations (e.g., vertical and horizontal). In examples disclosed herein, the APT power amplifier apparatus can be configured to employ a single power management integrated circuit (PMIC) to provide an APT voltage to all of the power amplifier circuits for amplifying the RF signal(s). By employing a single PMIC in the APT power amplifier apparatus, it is possible to reduce footprint, power consumption, and costs of the APT power amplifier apparatus.

Abstract: An inverted group delay circuit is provided. The inverted group delay circuit can offset a group delay between a pair of signals. In a non-limiting example, the inverted group delay circuit can be configured to offset a group delay (e.g., negative group delay) between a time-variant voltage and a time-variant envelope of an analog signal. More specifically, the inverted group delay circuit can output an inverted time-variant voltage having an opposing phase and time-adjusted relative to the time-variant voltage to thereby offset the group delay between the time-variant voltage and the time-variant envelope. As such, the inverted group delay circuit can be provided in a power management integrated circuit (PMIC) to improve timing alignment between a time-variant voltage(s) and a time-variant analog signal(s) at a power amplifier(s), thus helping to reduce potential amplitude distortion when the analog signal(s) is amplified by the power amplifier(s).

Abstract: A power management circuit operable with group delay is provided. In embodiments disclosed herein, the power management circuit includes a voltage processing circuit configured to receive a first time-variant target voltage having a first group delay relative to a time-variant target voltage and a second time-variant target voltage having a second group delay relative to the time-variant target voltage. Accordingly, the voltage processing circuit generates a windowed time-variant target voltage higher than or equal to a highest one of the first time-variant target voltage and the second time-variant target voltage in a group delay tolerance window(s) defined by the first group delay and the second group delay. As a result, the power management circuit can generate a time-variant voltage based on the windowed time-variant target voltage to help a power amplifier to avoid amplitude clipping when amplifying an analog signal.

Abstract: Maximum voltage detection in a power management circuit is provided. In embodiments disclosed herein, the power management circuit includes a voltage processing circuit configured to receive a first time-variant target voltage having a first group delay relative to a time-variant target voltage and a second time-variant target voltage having a second group delay relative to the time-variant target voltage. The voltage processing circuit includes a maximum signal detector circuit configured to generate a windowed time-variant target voltage that is higher than or equal to a highest one of the first time-variant target voltage and the second time-variant target voltage in a group delay tolerance window(s) defined by the first group delay and the second group delay. In this regard, the windowed time-variant target voltage can tolerate a certain amount of group delay within the group delay tolerance window(s).

Abstract: Envelope tracking power supply circuitry includes a look up table (LUT) configured to provide a target supply voltage based on a power envelope measurement. The target supply voltage is dynamically adjusted based on a delay between the power envelope of an RF signal and a provided envelope tracking supply voltage. The envelope tracking supply voltage is generated from the adjusted target supply voltage in order to synchronize the envelope tracking supply voltage with the power envelope of the RF signal.

Abstract: An envelope tracking (ET) radio frequency (RF) front-end circuit is provided. The ET RF front-end circuit includes an ET integrated circuit(s) (ETIC(s)), a local transceiver circuit, a target voltage circuit(s), and a number of power amplifiers. The local transceiver circuit receives an input signal(s) from a coupled baseband transceiver and generates a number of RF signals. The target voltage circuit(s) generates a time-variant ET target voltage(s) based on the input signal(s). The ETIC(s) generates multiple ET voltages based on the time-variant ET target voltage(s). The power amplifiers amplify the RF signals based on the ET voltages. Given that the time-variant ET target voltage(s) is generated inside the self-contained ET RF front-end circuit, it is possible to reduce distortion in the time-variant ET target voltage(s), thus helping to improve operating efficiency of the power amplifiers, especially when the RF signals are modulated with a higher modulation bandwidth (e.g., ?200 MHz).

Abstract: RF circuitry, which includes a first acoustic RF resonator (ARFR) and a first compensating ARFR, is disclosed. A first inductive element is coupled between the first compensating ARFR and a first end of the first ARFR. A second inductive element is coupled between the first compensating ARFR and a second end of the first ARFR. The first compensating ARFR, the first inductive element, and the second inductive element at least partially compensate for a parallel capacitance of the first ARFR.

Abstract: An average power tracking (APT) power amplifier apparatus is provided. In a non-limiting example, the APT power amplifier apparatus includes multiple sets of power amplifier circuits configured to amplify a radio frequency (RF) signal(s) for transmission in different polarizations (e.g., vertical and horizontal). In examples disclosed herein, the APT power amplifier apparatus can be configured to employ a single power management integrated circuit (PMIC) to provide an APT voltage to all of the power amplifier circuits for amplifying the RF signal(s). By employing a single PMIC in the APT power amplifier apparatus, it is possible to reduce footprint, power consumption, and costs of the APT power amplifier apparatus.

Abstract: A power amplifier apparatus supporting reverse intermodulation product (rIMD) cancellation is provided. The power amplifier apparatus includes an amplifier circuit configured to amplify and output a radio frequency (RF) signal for transmission via an antenna port. The antenna port may receive a reverse interference signal, which may interfere with the RF signal to create a rIMD(s) that can fall within an RF receive band(s). A reverse coupling circuit is provided in the power amplifier apparatus to generate an interference cancellation signal based on the reverse interference signal. The amplifier circuit is configured to amplify the interference cancellation signal and the RF signal to create an intermodulation product(s) to suppress the rIMD(s) to a determined threshold. By suppressing the rIMD(s) in the power amplifier apparatus, it is possible to support concurrent transmissions and receptions in a number of RF spectrums while in compliance with stringent regulatory spurious emissions (SEM) requirements.

Abstract: A microelectromechanical systems (MEMS) switch die having an N number of radio frequency (RF) MEMS switches, each having a anchored beam with a switch contact, a gate, and a terminal contact is disclosed. Also included is a MEMS-based decoder having logic gates comprised of logic MEMS switches that are configured to decode the coded signals to determine which of the N number of RF MEMS switches to open and close, apply a higher level gate voltage to each gate of the RF MEMS switches determined to be closed, wherein the higher gate voltage electrostatically pulls the anchored beam and brings the switch contact into electrical contact with the terminal contact, and apply a lower gate voltage to each gate of the RF MEMS switches to be opened, wherein the lower gate voltage releases the anchored beam and allows the switch contact to break electrical contact with the terminal contact.

Abstract: Embodiments of radio frequency (RF) filtering circuitry are disclosed. In one embodiment, the RF filtering circuitry includes a first port, a second port, a first RF filter path, and a second RF filter path. The first RF filter path is connected between the first port and the second port and includes at least a pair of weakly coupled resonators. The weakly coupled resonators are configured such that a first transfer response between the first port and the second port defines a first passband. The second RF filter path is coupled to the first RF filter path and is configured such that the first transfer response between the first port and the second port defines a stopband adjacent to the first passband without substantially increasing ripple variation of the first passband defined by the first transfer response.

Abstract: Radio frequency (RF) amplifier circuitry includes an input node, an output node, an amplifier, and bootstrap circuitry. The amplifier includes a control node coupled to the input node, a first amplifier node coupled to the output node, and a second amplifier node coupled to a fixed potential. The amplifier is configured to receive an input signal having a first frequency at the control node and change an impedance between the first amplifier node and the second amplifier node based on the input signal. The bootstrap circuitry is coupled between the control node and the second amplifier node. The bootstrap circuitry is configured to provide a low impedance path between the control node and the second amplifier node for signals having a second frequency that is equal to about twice the first frequency and provide a high impedance path for signals having a frequency outside the second frequency.

Abstract: Radio frequency (RF) amplifier circuitry includes an input node, an output node, an amplifier, and bootstrap circuitry. The amplifier includes a control node coupled to the input node, a first amplifier node coupled to the output node, and a second amplifier node coupled to a fixed potential. The amplifier is configured to receive an input signal having a first frequency at the control node and change an impedance between the first amplifier node and the second amplifier node based on the input signal. The bootstrap circuitry is coupled between the control node and the second amplifier node. The bootstrap circuitry is configured to provide a low impedance path between the control node and the second amplifier node for signals having a second frequency that is equal to about twice the first frequency and provide a high impedance path for signals having a frequency outside the second frequency.

Abstract: A microelectromechanical systems (MEMS) switch die having an N number of radio frequency (RF) MEMS switches, each having a anchored beam with a switch contact, a gate, and a terminal contact is disclosed. Also included is a MEMS-based decoder having logic gates comprised of logic MEMS switches that are configured to decode the coded signals to determine which of the N number of RF MEMS switches to open and close, apply a higher level gate voltage to each gate of the RF MEMS switches determined to be closed, wherein the higher gate voltage electrostatically pulls the anchored beam and brings the switch contact into electrical contact with the terminal contact, and apply a lower gate voltage to each gate of the RF MEMS switches to be opened, wherein the lower gate voltage releases the anchored beam and allows the switch contact to break electrical contact with the terminal contact.

Abstract: A stacked field-effect transistor (FET) switch is disclosed. The stacked FET switch has a first FET device stack that is operable in an on-state and in an off-state and is made up of a first plurality of FET devices coupled in series between a first port and a second port, wherein the first FET device stack has a conductance that decreases with increasing voltage between the first port and the second port. The stacked FET switch also includes a second FET device stack that is operable in the on-state and in the off-state and is made up of a second plurality of FET devices coupled in series between the first port and the second port, wherein the second FET device stack has a conductance that increases with increasing voltage between the first port and the second port.