Abstract: A notification system is provided including a first alert device configured to transmit and receive alerts conforming to a long range, low energy consumption point to point or mesh communication protocol and at least one additional alert device configured to transmit and receive alerts conforming to the protocol. The first alert device is configured to transmit a network creation ping using the protocol, the network creation ping receivable by at least one additional alert device approved to join a decentralized network. At least one additional alert device receiving the network creation ping is configured to pair with the first alert device thereby establishing the decentralized network. The first alert device and each additional alert device in the decentralized network is configured to transmit an alert directly to at least one other alert device in the decentralized network using the protocol.

Abstract: An application processor coupled to a Static Random Access Memory (SRAM) interfaces with a graphics accelerator. A Dynamic Random Access Memory (DRAM) stores frame buffer data that may be transferred to a display through a switch located on the graphics accelerator in normal operation. In a power savings mode, the DRAM may be powered down and a copied frame buffer data stored in the SRAM may be transferred to the display through the switch.

Abstract: Local memory associated with one or more companion devices within a system is mapped into a system memory for use by an application processor.

Abstract: An accelerated dual display enabling a user to dynamically decide which graphics subsystem will run which display on a handheld device. The dual display system has an application processor and an external chip. A crossbar located in the external chip connects the application processor to the external chip. Displays are connected to the crossbar.

Abstract: An application processor coupled to a Static Random Access Memory (SRAM) interfaces with a graphics accelerator. A Dynamic Random Access Memory (DRAM) stores frame buffer data that may be transferred to a display through a switch located on the graphics accelerator in normal operation. In a power savings mode, the DRAM may be powered down and a copied frame buffer data stored in the SRAM may be transferred to the display through the switch.

Abstract: The present invention is a method and apparatus to map first graphics pins into second graphics pins. A first plurality of data and command pins corresponding to data and command signals in a first graphics mode is mapped into a second plurality of data and command pins corresponding to data and command signals in a second graphics mode. The first and second graphics modes are supported by a first chipset. The second graphics mode is supported by a second chipset. A detector pin strappable to a logic level to indicate an external graphics card is used in the first graphics mode is mapped into a first pin corresponding to a first signal of the second graphics mode. The first signal is ignored by the second chipset during initialization.