Abstract: A package comprising a first substrate; a first integrated device coupled to the first substrate; an interconnection die coupled to the first substrate; a second substrate coupled to the first substrate through the interconnection die such that the first integrated device and the interconnection die are located between the first substrate and the second substrate; and an encapsulation layer coupled to the first substrate and the second substrate, wherein the encapsulation layer is located between the first substrate and the second substrate.

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer and a plurality of interconnects comprising a bump pad interconnect. The bump pad interconnect comprises a profile cross section that has a trapezoid shape. The integrated device is coupled to the substrate through the bump pad interconnect. The bump pad interconnect is located in a cavity of the at least one dielectric layer of the substrate.

Abstract: Examples herein include die to metallization structure connections that eliminate the solder joint to reduce the resistance and noise on the connection. In one example, a first die is attached to a metallization layer by a plurality of copper interconnections and a second is attached to the metallization layer opposite the first die through another plurality of copper interconnections. In this example, the copper interconnects may connect the respective die to a metallization structure in the metallization layer.

Abstract: A package that includes a substrate and an integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a first material, and a plurality of surface interconnects coupled to the plurality of interconnects. The plurality of surface interconnects comprises a second material. A surface of the plurality of surface interconnects is planar with a surface of the substrate. The integrated device is coupled to the plurality of surface interconnects of the substrate through a plurality of pillar interconnects and a plurality of solder interconnects.

Abstract: Certain aspects of the present disclosure generally relate to an embedded trace substrate (ETS) with one or more passive components embedded therein. Such an ETS may provide shorter routing, smaller loop area, and lower parasitics between a semiconductor die and a land-side passive component embedded in the ETS. One example embedded trace substrate generally includes a core, a first insulating material disposed above the core and having a first metal pattern embedded therein, a second insulating material disposed below the core and having a second metal pattern embedded therein, and one or more passive components embedded in the core.

Abstract: Aspects disclosed herein include a device including a bump pad structure and methods for fabricating the same. The device includes a bump pad. The device also includes a first trace adjacent the bump pad, where a first trace top surface is recessed a first recess distance from a bump pad top surface. The device also includes a second trace adjacent the first trace, covered at least in part by a solder resist. The device also includes a substrate, where the bump pad, the first trace, and the second trace are each formed on a portion of the substrate.

Abstract: A package comprising a first integrated device comprising a first plurality of under bump metallization interconnects; a second integrated device comprising a second plurality of under bump metallization interconnects; a bridge coupled to the first integrated device and the second integrated device; an encapsulation layer at least partially encapsulating the first integrated device, the second integrated device, and the bridge; a metallization portion located over the first integrated device, the second integrated device, the bridge and the encapsulation layer, where the metallization portion includes at least one dielectric layer and a plurality of metallization interconnects; a first plurality of pillar interconnects coupled to the first plurality of under bump metallization interconnects, the first plurality of interconnects located in the encapsulation layer; and a second plurality of pillar interconnects coupled to the second plurality of under bump metallization interconnects, the second plurality of pi

Abstract: Integrated circuit (IC) packages employing split, double-sided IC metallization structures to facilitate a semiconductor die module employing stacked dice, and related fabrication methods are disclosed. Multiple IC dice in the IC package are stacked and bonded together in a back-to-back, top and bottom IC die configuration in an IC die module, which can minimize the height of the IC package. The metallization structure is split between separate top and bottom metallization structures adjacent to respective top and bottom surfaces of the IC die module to facilitate die-to-die and external electrical connections to the dice. The top and bottom metallization structures can be double-sided by exposing substrate interconnects on respective inner and outer surfaces for respective die and external electrical interconnections. In other aspects, a compression bond is included between the IC dice mounted together in a back-to-back configuration to further minimize the overall height of the IC package.

Abstract: A package that includes a substrate and an integrated device. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a first material, and a plurality of surface interconnects coupled to the plurality of interconnects. The plurality of surface interconnects comprises a second material. A surface of the plurality of surface interconnects is planar with a surface of the substrate. The integrated device is coupled to the plurality of surface interconnects of the substrate through a plurality of pillar interconnects and a plurality of solder interconnects.

Abstract: A package that includes a first substrate, an integrated device coupled to the first substrate, a second substrate coupled to the integrated device, and an encapsulation layer located between the first substrate and the second substrate. The second substrate is configured to operate as a heat spreader. The second substrate is configured to be free of an electrical connection with the integrated device.

Abstract: Aspects disclosed herein include a device including a bump pad structure and methods for fabricating the same. The device includes a bump pad. The device also includes a first trace adjacent the bump pad, where a first trace top surface is recessed a first recess distance from a bump pad top surface. The device also includes a second trace adjacent the first trace, covered at least in part by a solder resist. The device also includes a substrate, where the bump pad, the first trace, and the second trace are each formed on a portion of the substrate.

Abstract: Examples herein include die to metallization structure connections that eliminate the solder joint to reduce the resistance and noise on the connection. In one example, a first die is attached to a metallization layer by a plurality of copper interconnections and a second is attached to the metallization layer opposite the first die through another plurality of copper interconnections. In this example, the copper interconnects may connect the respective die to a metallization structure in the metallization layer.

Abstract: Certain aspects of the present disclosure generally relate to an embedded trace substrate (ETS) with one or more passive components embedded therein. Such an ETS may provide shorter routing, smaller loop area, and lower parasitics between a semiconductor die and a land-side passive component embedded in the ETS. One example embedded trace substrate generally includes a core, a first insulating material disposed above the core and having a first metal pattern embedded therein, a second insulating material disposed below the core and having a second metal pattern embedded therein, and one or more passive components embedded in the core.

Abstract: Integrated circuit (IC) packages employing split, double-sided IC metallization structures to facilitate a semiconductor die module employing stacked dice, and related fabrication methods are disclosed. Multiple IC dice in the IC package are stacked and bonded together in a back-to-back, top and bottom IC die configuration in an IC die module, which can minimize the height of the IC package. The metallization structure is split between separate top and bottom metallization structures adjacent to respective top and bottom surfaces of the IC die module to facilitate die-to-die and external electrical connections to the dice. The top and bottom metallization structures can be double-sided by exposing substrate interconnects on respective inner and outer surfaces for respective die and external electrical interconnections. In other aspects, a compression bond is included between the IC dice mounted together in a back-to-back configuration to further minimize the overall height of the IC package.

Abstract: Integrated circuit (IC) packages employing split, double-sided IC metallization structures to facilitate a semiconductor die (“IC die”) module employing stacked dice, and related fabrication methods are disclosed. Multiple IC dice in the IC package are stacked and bonded together in a back-to-back, top and bottom IC die configuration in an IC die module, which can minimize the overall height of the IC package. The metallization structure is split between separate top and bottom metallization structures adjacent to respective top and bottom surfaces of the IC die module to facilitate die-to-die and external electrical connections to the dice. The top and bottom metallization structures can be double-sided by exposing substrate interconnects on respective inner and outer surfaces for respective die and external electrical interconnections.

Abstract: A package that includes a first substrate, an integrated device coupled to the first substrate, a second substrate coupled to the integrated device, and an encapsulation layer located between the first substrate and the second substrate. The second substrate is configured to operate as a heat spreader. The second substrate is configured to be free of an electrical connection with the integrated device.

Abstract: A device that includes a die and a substrate coupled to the die. The substrate includes a dielectric layer and a plurality of embedded interconnects. Each embedded interconnect located through a first planar surface of the substrate such that a first portion of the embedded interconnect is located within the dielectric layer and a second portion of the embedded interconnect is external of the dielectric layer. In some implementations, the substrate includes a core layer. In some implementations, the dielectric layer and the plurality of embedded interconnects may be part of a build up layer of the substrate.

Abstract: A device that includes a die and a substrate coupled to the die. The substrate includes a dielectric layer and a plurality of embedded interconnects. Each embedded interconnect located through a first planar surface of the substrate such that a first portion of the embedded interconnect is located within the dielectric layer and a second portion of the embedded interconnect is external of the dielectric layer. In some implementations, the substrate includes a core layer. In some implementations, the dielectric layer and the plurality of embedded interconnects may be part of a build up layer of the substrate.

Abstract: Exemplary packages according to some aspects of the disclosure may include a symmetric structure with a thick core for embedded trace substrates. The packages may include an embedded third dielectric layer for preventing bump shorts or trace peel off between fine bump areas with a solder resist trench. This may allow fine bump pitches with escape lines (traces) on flip chip bump array (FCBGA) applications, for example.