Abstract: A semiconductor device is disclosed. One embodiment provides an arrangement of a plurality of semiconductor chips arranged side by side in a spaced apart relationship. A first material fills at least partly the spacings between adjacent semiconductor chips. A second material is arranged over the semiconductor chips and the first material. A coefficient of thermal expansion of the first material is selected to adapt the lateral thermal expansion of the arrangement in a plane intersecting the first material and the semiconductor chips to the lateral thermal expansion of the arrangement in a plane intersecting the second material.

Abstract: A semiconductor device is disclosed. One embodiment provides an arrangement of a plurality of semiconductor chips arranged side by side in a spaced apart relationship. A first material fills at least partly the spacings between adjacent semiconductor chips. A second material is arranged over the semiconductor chips and the first material. A coefficient of thermal expansion of the first material is selected to adapt the lateral thermal expansion of the arrangement in a plane intersecting the first material and the semiconductor chips to the lateral thermal expansion of the arrangement in a plane intersecting the second material.

Abstract: A method for removing structures from a substrate is described. The method includes providing a substrate that has the structures that must be removed, applying a sacrifice layer, and removing the structures and the sacrifice layer in a polishing step. The method has the advantage that the sacrifice layer surrounds the structures that must be removed and stabilizes them, so that the structures can be eroded slowly and successively in the subsequent polishing step without breaking off. This prevents a smearing of the material of the structures such as occurs given direct polishing without a sacrifice layer.

Abstract: A method for producing an integrated semiconductor memory configuration includes forming two capacitor modules for each selection transistor from the front and rear side of the substrate wafer respectively. Thus, a higher packing density of memory cells is engendered by the utilization of the rear side of the wafer. A twofold memory read signal can be used for the same cell surface area. Conditions in addition to “0” or “1” can also be saved for each selection transistor in a ferroelectric memory configuration, if the two capacitor modules have a different structure in terms of layer thickness, surface area, or material.

Abstract: A method for producing an integrated semiconductor memory configuration includes forming two capacitor modules for each selection transistor from the front and rear side of the substrate wafer respectively. Thus, a higher packing density of memory cells is engendered by the utilization of the rear side of the wafer. A twofold memory read signal can be used for the same cell surface area. Conditions in addition to “0” or “1” can also be saved for each selection transistor in a ferroelectric memory configuration, if the two capacitor modules have a different structure in terms of layer thickness, surface area, or material.

Abstract: The integrated ferroelectric or DRAM semiconductor memory configuration has memory cells each with a selection transistor and a capacitor module that can be addressed by the selection transistor. The capacitors of successive memory cells are formed alternately on the front and rear sides of a substrate wafer.

Abstract: A method of producing a ferroelectric semiconductor memory, includes forming a switching transistor on a semiconductor substrate, applying an insulating layer to the switching transistor and then forming a storage capacitor, with electrodes of platinum and a ferroelectric or paraelectric dielectric, on the insulating layer. In order to protect the dielectric from being penetrated by hydrogen during further process steps, a first barrier layer is embedded into the insulating layer and, after completion of the storage capacitor, a second barrier layer, which bonds with the first barrier layer, is deposited.

Abstract: The integrated ferroelectric or DRAM semiconductor memory configuration has memory cells each with a selection transistor and a capacitor module that can be addressed by the selection transistor. The capacitors of successive memory cells are formed alternately on the front and rear sides of a substrate wafer.

Abstract: A method for removing structures from a substrate is described. The method includes providing a substrate that has the structures that must be removed, applying a sacrifice layer, and removing the structures and the sacrifice layer in a polishing step. The method has the advantage that the sacrifice layer surrounds the structures that must be removed and stabilizes them, so that the structures can be eroded slowly and successively in the subsequent polishing step without breaking off. This prevents a smearing of the material of the structures such as occurs given direct polishing without a sacrifice layer.

Abstract: When fabricating a DRAM memory cell with a switching transistor and a storage capacitor containing a ferroelectric dielectric and platinum electrodes, a conductive protective layer is applied to the upper electrode at least in the region of a contact opening formed in an insulation layer, so that tungsten can be filled into the contact opening with a chemical vapor deposition in an H2 atmosphere without the dielectric being reduced by the hydrogen under the catalytic action of the platinum. A semiconductor component is also provided.

Abstract: A method of producing a ferroelectric semiconductor memory, includes forming a switching transistor on a semiconductor substrate, applying an insulating layer to the switching transistor and then forming a storage capacitor, with electrodes of platinum and a ferroelectric or paraelectric dielectric, on the insulating layer. In order to protect the dielectric from being penetrated by hydrogen during further process steps, a first barrier layer is embedded into the insulating layer and, after completion of the storage capacitor, a second barrier layer, which bonds with the first barrier layer, is deposited.