Patents by Inventor Marcus M. G. Quax
Marcus M. G. Quax has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9184953Abstract: A programmable signal processing circuit has an instruction processing circuit (23, 24. 26), which has an instruction set that comprises a demapping instruction. The instruction processing circuit (23, 24, 26) has an operand input (30a) for receiving a complex number operand of the demapping instruction from a register file (22) and a result output (34) for writing a demapping result of the demapping instruction to the register file (22). The instruction processing circuit (23, 24, 26) determines at least four bit metrics in response to the demapping instruction, each indicating a relative position of the complex number relative to respective border line in a complex plane. The instruction processing circuit (23, 24, 26) writes a combination of the at least four bit metrics together to the result output (34) in the demapping result.Type: GrantFiled: December 13, 2005Date of Patent: November 10, 2015Assignee: INTEL CORPORATIONInventors: Ingolf Held, Marcus M. G. Quax, Paulus W. F. Gruijters
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Patent number: 8433881Abstract: A programmable signal processing circuit is used to (de-)interleave a data stream. Data from the signal stream is stored in a data memory (28) and read in a different sequence. The programmable signal processing circuit is used for computing addresses, for use in said storing and/or reading. The programmable signal processing circuit has an instruction set that contains an instruction to compute the addresses from preceding addresses that have been used for said storing and/or reading. In response to the instruction the programmable signal processing circuit permutes positions of a plurality of bits from the old address operand and forms of a bit of the new address result as a logic function of a combination of bits from the old address operand. Successive addresses are formed by means of repeated execution of a program loop that contains an address update instruction for computing the addresses.Type: GrantFiled: January 24, 2012Date of Patent: April 30, 2013Assignee: Intel Benelux B.V.Inventors: Paulus W. F. Gruijters, Marcus M. G. Quax, Ingolf Held
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Publication number: 20120120310Abstract: A programmable signal processing circuit is used to (de-)interleave a data stream. Data from the signal stream is stored in a data memory (28) and read in a different sequence. The programmable signal processing circuit is used for computing addresses, for use in said storing and/or reading. The programmable signal processing circuit has an instruction set that contains an instruction to compute the addresses from preceding addresses that have been used for said storing and/or reading. In response to the instruction the programmable signal processing circuit permutes positions of a plurality of bits from the old address operand and forms of a bit of the new address result as a logic function of a combination of bits from the old address operand. Successive addresses are formed by means of repeated execution of a program loop that contains an address update instruction for computing the addresses.Type: ApplicationFiled: January 24, 2012Publication date: May 17, 2012Applicant: Silicon Hive B.V.Inventors: Paulus W. F. Gruijters, Marcus M.G. Quax, Ingolf Held
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Patent number: 8108651Abstract: A programmable signal processing circuit is used to (de-)interleave a data stream. Data from the signal stream is stored in a data memory (28) and read in a different sequence. The programmable signal processing circuit is used for computing addresses, for use in said storing and/or reading. The programmable signal processing circuit has an instruction set that contains an instruction to compute the addresses from preceding addresses that have been used for said storing and/or reading. In response to the instruction the programmable signal processing circuit permutes positions of a plurality of bits from the old address operand and forms of a bit of the new address result as a logic function of a combination of bits from the old address operand. Successive addresses are formed by means of repeated execution of a program loop that contains an address update instruction for computing the addresses.Type: GrantFiled: December 13, 2005Date of Patent: January 31, 2012Assignee: Silicon Hive B.V.Inventors: Paulus W. F. Gruijters, Marcus M. G. Quax, Ingolf Held
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Patent number: 7853860Abstract: A programmable signal processing circuit has an instruction processing circuit (23, 24, 26), with an instruction set that comprises a depuncture instruction. The instruction processing circuit (23, 24, 26) forms the depuncture result by copying bit metrics from a bit metrics operand and inserting one or more predetermined bit metric values between the bit metrics from the bit metric operand in the depuncture result. The instruction processing circuit (23, 24, 26) changes the relative locations of the copied bit metrics with respect to each other in the depuncture result as compared to the relative locations of the copied bit metrics with respect to each other in the bit metric operand, to an extent needed for accommodating the inserted predetermined bit metric value or values.Type: GrantFiled: December 13, 2005Date of Patent: December 14, 2010Assignee: Silicon Hive B.V.Inventors: Paulus W. F. Gruijters, Marcus M. G. Quax
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Publication number: 20100039567Abstract: A programmable signal processing circuit is used to (de-)interleave a data stream. Data from the signal stream is stored in a data memory (28) and read in a different sequence. The programmable signal processing circuit is used for computing addresses, for use in said storing and/or reading. The programmable signal processing circuit has an instruction set that contains an instruction to compute the addresses from preceding addresses that have been used for said storing and/or reading. In response to the instruction the programmable signal processing circuit permutes positions of a plurality of bits from the old address operand and forms of a bit of the new address result as a logic function of a combination of bits from the old address operand. Successive addresses are formed by means of repeated execution of a program loop that contains an address update instruction for computing the addresses.Type: ApplicationFiled: December 13, 2005Publication date: February 18, 2010Applicant: KONINKLIJKE PHILIPS ELECTRONICS, N.V.Inventors: Paulus W.F. Gruijters, Marcus M.G. Quax, Ingolf Held
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Publication number: 20100017453Abstract: A programmable signal processing circuit has an instruction processing circuit (23, 24. 26), which has an instruction set that comprises a demapping instruction. The instruction processing circuit (23, 24, 26) has an operand input (30a) for receiving a complex number operand of the demapping instruction from a register file (22) and a result output (34) for writing a demapping result of the demapping instruction to the register file (22). The instruction processing circuit (23, 24, 26) determines at least four bit metrics in response to the demapping instruction, each indicating a relative position of the complex number relative to respective border line in a complex plane. The instruction processing circuit (23, 24, 26) writes a combination of the at least four bit metrics together to the result output (34) in the demapping result.Type: ApplicationFiled: December 13, 2005Publication date: January 21, 2010Applicant: KONINKLIJKE PHILIPS ELECTRONICS, N.V.Inventors: Ingolf Held, Marcus M.G. Quax, Paulus W.F. Gruijters
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Publication number: 20090287911Abstract: A programmable signal processing circuit has an instruction processing circuit (23, 24, 26), with an instruction set that comprises a depuncture instruction. The instruction processing circuit (23, 24, 26) forms the depuncture result by copying bit metrics from a bit metrics operand and inserting one or more predetermined bit metric values between the bit metrics from the bit metric operand in the depuncture result. The instruction processing circuit (23, 24, 26) changes the relative locations of the copied bit metrics with respect to each other in the depuncture result as compared to the relative locations of the copied bit metrics with respect to each other in the bit metric operand, to an extent needed for accommodating the inserted predetermined bit metric value or values.Type: ApplicationFiled: December 13, 2005Publication date: November 19, 2009Applicant: KONINKLIJKE PHILIPS ELECTRONICS, N.V.Inventors: Paulus W.F. Gruijters, Marcus M.G. Quax