Abstract: Systems and methods are disclosed for magnetoresistive asymmetry (MRA) compensation using a digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end circuit, and performing analog offset compensation to constrain the extrema of the analog signal to adjust a dynamic range based on an input range of an analog-to-digital converter (ADC), rather than to modify the analog signal to have a zero mean. The method may further comprise converting the analog signal to a digital sample sequence via the ADC; performing, via a digital MRA compensation circuit, digital MRA compensation on the digital sample sequence; receiving, via a digital backend (DBE) subsystem, the digital sample sequence prior to digital MRA compensation; and generating, via a DBE, a bit sequence corresponding to the analog signal based on an output of the DBE subsystem and an output of the digital MRA compensation circuit.

Abstract: A cyclo-stationary characteristic of a communications channel and/or storage media is determined. The cyclo-stationary characteristic has K-cycles, K>1. Markov transition probabilities are determined that depend on a discrete phase ?=t mod K, wherein t is a discrete time value. An encoder to optimize the Markov transition probabilities for encoding data sent through the communications channel and/or stored on the storage media. The optimized Markov transition probabilities are used to decode the data from the communication channel and/or read from the storage media.

Abstract: Systems and methods are disclosed for magnetoresistive asymmetry compensation using a hybrid analog and digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end (CTFE) circuit, and performing, via the CTFE circuit, first magnetoresistive asymmetry (MRA) compensation on the analog signal to adjust the dynamic range of the analog signal based on an input range of an analog-to-digital converter (ADC). The method may further comprise converting the analog signal to a digital sample sequence via the ADC, and performing, via a digital MRA compensation circuit, second MRA compensation to correct residual MRA in the digital sample sequence. Offset compensation may also be performed in both the analog and digital domains.

Abstract: An error recovery process provides for selecting a first recovery scheme for a decoding attempt on a first subset of a set of failed data blocks read from a data track; selecting a second different recovery scheme for a decoding attempt on a second subset of the set of failed data blocks read from the data track; and during a single revolution of the data track, performing operations to decode a first subset of the failed data blocks according to the first recovery scheme operations to decode the second subset of the failed data blocks according to the second different recovery scheme.

Abstract: Systems and methods are disclosed for synchronous writing of a grain patterned medium. The systems and methods can be implemented within a data storage device having a grain patterned medium. Further, a calibration process to determine a count of bits between servo wedges can be implemented in manufacturing, within the data storage device, or both. In some examples, the data storage device, during operation, can utilize the count of bits to perform synchronous writing, determine write errors, or both. Further, the servo wedge of the grain patterned medium may be patterned with a same or similar grain pattern as the data area that follows the servo wedge. Such a data storage device can implement a single clock for reading a servo wedge and writing a data area.

Abstract: A one-shot state transition decoder receives a codeword having N-bits. The decoder reads a first D-bits of the codeword to determine a stitching location d within the codeword. The stitching location identifies a start bit of unencoded data in the codeword. The codeword is decoded into an output buffer for user data of L bits, where N>L. Parameters of the decoder are set before the decoding, including setting a length of the codeword to N?L+d and a number of expected decoded bits to d. The decoding including decoding the d bits based on a set of state transition probabilities and copying decoded bits into the output buffer, the unencoded data being copied to the end of the output buffer.

Abstract: Systems and methods are disclosed for magnetoresistive asymmetry (MRA) compensation using a digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end (CTFE) circuit, and performing analog offset compensation to constrain an extremum of the analog signal to adjust a dynamic range based on an input range of an analog-to-digital converter (ADC), rather than to modify the analog signal to have a zero mean. The method may further comprise converting the analog signal to a digital sample sequence via the ADC; performing, via a digital MRA compensation circuit, digital MRA compensation on the digital sample sequence; receiving, via a digital backend (DBE) subsystem, the digital sample sequence prior to digital MRA compensation; and generating, via a DBE, a bit sequence corresponding to the analog signal based on an output of the DBE subsystem and an output of the digital MRA compensation circuit.

Abstract: A cyclo-stationary characteristic of a communications channel and/or storage media is determined. The cyclo-stationary characteristic has K-cycles, K > 1. Markov transition probabilities are determined that depend on a discrete phase ?=t mod K, wherein t is a discrete time value. An encoder to optimize the Markov transition probabilities for encoding data sent through the communications channel and/or stored on the storage media. The optimized Markov transition probabilities are used to decode the data from the communication channel and/or read from the storage media.

Abstract: Systems and methods are disclosed for synchronous writing of a grain patterned medium. The systems and methods can be implemented within a data storage device having a grain patterned medium. Further, a calibration process to determine a count of bits between servo wedges can be implemented in manufacturing, within the data storage device, or both. In some examples, the data storage device, during operation, can utilize the count of bits to perform synchronous writing, determine write errors, or both. Further, the servo wedge of the grain patterned medium may be patterned with a same or similar grain pattern as the data area that follows the servo wedge. Such a data storage device can implement a single clock for reading a servo wedge and writing a data area.

Abstract: A plurality of configuration sets are used with a detector coupled to a decoder. A processor is coupled to the memory registers and the detector and operable to load a first one of the configuration sets into the detector. The detector to attempts detection of the bits in the digital stream for a first iteration between the detector and the decoder using the first configuration set. After the first iteration, a second one of the configuration sets is loaded into the detector. The second configuration set is different than the first configuration set. The detector to attempts detection of the bits in the digital stream for a second iteration between the detector and the decoder using the second configuration set.

Abstract: Systems and methods are disclosed for synchronous writing of a grain patterned medium. The systems and methods can be implemented within a data storage device having a grain patterned medium. Further, a calibration process to determine a count of bits between servo wedges can be implemented in manufacturing, within the data storage device, or both. In some examples, the data storage device, during operation, can utilize the count of bits to perform synchronous writing, determine write errors, or both. Further, the servo wedge of the grain patterned medium may be patterned with a same or similar grain pattern as the data area that follows the servo wedge. Such a data storage device can implement a single clock for reading a servo wedge and writing a data area.

Abstract: A one-shot state transition decoder receives a codeword having N-bits. The decoder reads a first D-bits of the codeword to determine a stitching location d within the codeword. The stitching location identifies a start bit of unencoded data in the codeword. The codeword is decoded into an output buffer for user data of L bits, where N>L. Parameters of the decoder are set before the decoding, including setting a length of the codeword to N?L+d and a number of expected decoded bits to d. The decoding including decoding the d bits based on a set of state transition probabilities and copying decoded bits into the output buffer, the unencoded data being copied to the end of the output buffer.

Abstract: Systems and methods are disclosed for magnetoresistive asymmetry (MRA) compensation using a digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end (CTFE) circuit, and performing analog offset compensation to constrain an extremum of the analog signal to adjust a dynamic range based on an input range of an analog-to-digital converter (ADC), rather than to modify the analog signal to have a zero mean. The method may further comprise converting the analog signal to a digital sample sequence via the ADC; performing, via a digital MRA compensation circuit, digital MRA compensation on the digital sample sequence; receiving, via a digital backend (DBE) subsystem, the digital sample sequence prior to digital MRA compensation; and generating, via a DBE, a bit sequence corresponding to the analog signal based on an output of the DBE subsystem and an output of the digital MRA compensation circuit.

Abstract: Systems and methods are disclosed for magnetoresistive asymmetry compensation using a hybrid analog and digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end (CTFE) circuit, and performing, via the CTFE circuit, first magnetoresistive asymmetry (MRA) compensation on the analog signal to adjust the dynamic range of the analog signal based on an input range of an analog-to-digital converter (ADC). The method may further comprise converting the analog signal to a digital sample sequence via the ADC, and performing, via a digital MRA compensation circuit, second MRA compensation to correct residual MRA in the digital sample sequence. Offset compensation may also be performed in both the analog and digital domains.

Abstract: Systems and methods are disclosed for full utilization of a data path's dynamic range. In certain embodiments, an apparatus may comprise a circuit including a first filter to digitally filter and output a first signal, a second filter to digitally filter and output a second signal, a summing node, and a first adaptation circuit. The summing node combine the first signal and the second signal to generate a combined signal at a summing node output. The first adaptation circuit may be configured to receive the combined signal, and filter the first signal and the second signal to set a dynamic amplitude range of the combined signal at the summing node output by modifying a first coefficient of the first filter and a second coefficient of the second filter based on the combined signal.

Abstract: In a one-shot state transition encoder, L-bits of user data are received and encoded into a codeword of N-bits, wherein N>L. The encoding of the user data involves repeatedly performing: a) encoding a portion of user bits from the user data to a portion of encoded bits of the codeword based on a set of state transition probabilities, thereby reducing a size of a remaining buffer of the codeword and reducing a number of unencoded bits of the user data; and b) based on the number of unencoded bits of the user data being greater than or equal to the remaining buffer size of the codeword, terminating further encoding and storing the unencoded bits of the user data into the remaining buffer of the codeword.

Abstract: Systems and methods are disclosed for hardware-based read sample averaging in a data storage device. In one example, a read channel circuit including a buffer memory is configured to receive a read instruction to read a selected sector, obtain detected sample values for the selected sector, and determine whether the read instruction corresponds to a re-read operation for the selected sector based on determining whether there are stored samples for the selected sector already stored to a locked buffer entry of the buffer memory. When there are stored sample values stored to the locked buffer entry, the example read channel circuit determines the re-read operation is occurring, and performs read sample averaging based on the detected sample values and the stored sample values to produce averaged sample values. Other examples and configurations are also described.

Abstract: In one implementation, the disclosure provides a decoding system that concurrently executes a read sample combining recovery process and an iterative outer code (IOC) recovery process. Performing the read sample combining recovery process entails executing multiple rounds of logic that each provide for combining together different data samples read from a data block. The IOC recovery process is performed at least partially concurrent with the read sample combining recovery process and each round of the IOC recovery process is based on newly-updated data samples generated by the read sample combining recovery process.

Abstract: Systems and methods are disclosed for magnetoresistive asymmetry (MRA) compensation using a digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end (CTFE) circuit, and performing analog offset compensation to constrain an extremum of the analog signal to adjust a dynamic range based on an input range of an analog-to-digital converter (ADC), rather than to modify the analog signal to have a zero mean. The method may further comprise converting the analog signal to a digital sample sequence via the ADC; performing, via a digital MRA compensation circuit, digital MRA compensation on the digital sample sequence; receiving, via a digital backend (DBE) subsystem, the digital sample sequence prior to digital MRA compensation; and generating, via a DBE, a bit sequence corresponding to the analog signal based on an output of the DBE subsystem and an output of the digital MRA compensation circuit.

Abstract: In a one-shot state transition encoder, L-bits of user data are received and encoded into a codeword of N-bits, wherein N>L. The encoding of the user data involves repeatedly performing: a) encoding a portion of user bits from the user data to a portion of encoded bits of the codeword based on a set of state transition probabilities, thereby reducing a size of a remaining buffer of the codeword and reducing a number of unencoded bits of the user data; and b) based on the number of unencoded bits of the user data being greater than or equal to the remaining buffer size of the codeword, terminating further encoding and storing the unencoded bits of the user data into the remaining buffer of the codeword.