Abstract: Methods, devices and systems for improving travel planning, booking and viewing using an integrated travel platform are described. An example method includes presenting, by an integrated electronic travel platform to a user, a profile comprising a plurality of fields to receive a set of parameters associated with a trip that comprises a plurality of modalities, analyzing, using a shared ontology data structure, the profile to determine a plurality of options for each of the plurality of modalities, wherein each of the plurality of options conforms to the set of parameters for the corresponding modality, presenting, to the user, the plurality of options, receiving, from the user, a plurality of selections corresponding to one option from the plurality of options for each of the plurality of modalities, performing, while remaining within the integrated electronic travel platform, a booking operation for each of the plurality of selections.

Abstract: A low power biasing circuit for powering up split-rail electronic circuits includes an intermediate voltage generator at each pad which is supplied by a temporary supply voltage to generate a temporary intermediate voltage only when a power signal indicates that all external voltage rails are not safe, thereby reducing power consumption.

Abstract: An integrated circuit is capable of controlling a communication signal by using power ramp controlled communication buffer logic to generate an outgoing communication signal based on a detected voltage on a voltage source. The voltage source is necessary to supply power for power ramp controlled communication buffer logic. The voltage on the voltage source may be detected using power ramp sensor logic. The outgoing communication signal is based on a core logic output signal if the detected voltage is greater than or equal to a predetermined voltage level. If, the detected voltage is less than the predetermined voltage level, the outgoing communication signal is predetermined to be one of: a tristate outgoing communication signal, a logic one outgoing communication signal and a logic zero outgoing communication signal. Power ramp controlled communication buffer logic may also generate a core logic input signal based on an incoming communication signal in response to the detected voltage.

Abstract: A low power biasing circuit for powering up split-rail electronic circuits includes an intermediate voltage generator at each pad which is supplied by a temporary supply voltage to generate a temporary intermediate voltage only when a power signal indicates that all external voltage rails are not safe, thereby reducing power consumption.

Abstract: A method and apparatus for powering up an integrated circuit having a plurality of power domains each coupled to receive power from one of a plurality of power sources, where each power domain includes an internal power detector which senses the power of a plurality of power domains (VDD1, VDD2, VDD3, . . . , VDDn) and compares them to a reference voltage to generate a combined power good (PG) signal. The PG signal is combined with an external system power ok signal at a plurality of AND gate circuits which are respectively powered by the plurality of power domains, thereby generating a plurality of power status signals (POWER_OK) on the destination power domains.

Abstract: An integrated circuit is capable of controlling a communication signal by using power ramp controlled communication buffer logic to generate an outgoing communication signal based on a detected voltage on a voltage source. The voltage source is necessary to supply power for power ramp controlled communication buffer logic. The voltage on the voltage source may be detected using power ramp sensor logic. The outgoing communication signal is based on a core logic output signal if the detected voltage is greater than or equal to a predetermined voltage level. If, the detected voltage is less than the predetermined voltage level, the outgoing communication signal is predetermined to be one of: a tristate outgoing communication signal, a logic one outgoing communication signal and a logic zero outgoing communication signal. Power ramp controlled communication buffer logic may also generate a core logic input signal based on an incoming communication signal in response to the detected voltage.